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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-07-17 14:38:39 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-07-18 12:37:48 -0700 |
| commit | 6ae8aac19cdbdbd96d90f86e4d8505fe121bdf06 (patch) | |
| tree | 9c77c74007cd08c616cfa8f93f41067c8e82bf66 /gcc/common | |
| parent | f527b8233498b40c8a2c616b82265f2e58aba42a (diff) | |
| download | gcc-6ae8aac19cdbdbd96d90f86e4d8505fe121bdf06.zip gcc-6ae8aac19cdbdbd96d90f86e4d8505fe121bdf06.tar.gz gcc-6ae8aac19cdbdbd96d90f86e4d8505fe121bdf06.tar.bz2 | |
x86: Enable the GPR only instructions for -mgeneral-regs-only
For -mgeneral-regs-only, enable the GPR only instructions which are
enabled implicitly by SSE ISAs unless they have been disabled explicitly.
gcc/
PR target/101492
* common/config/i386/i386-common.c (ix86_handle_option): For
-mgeneral-regs-only, enable the GPR only instructions which are
enabled implicitly by SSE ISAs unless they have been disabled
explicitly.
gcc/testsuite/
PR target/101492
* gcc.target/i386/pr101492-1.c: New test.
* gcc.target/i386/pr101492-2.c: Likewise.
* gcc.target/i386/pr101492-3.c: Likewise.
* gcc.target/i386/pr101492-4.c: Likewise.
Diffstat (limited to 'gcc/common')
| -rw-r--r-- | gcc/common/config/i386/i386-common.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index e156cc3..76ab1a1 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -354,16 +354,39 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mgeneral_regs_only: if (value) { + HOST_WIDE_INT general_regs_only_flags = 0; + HOST_WIDE_INT general_regs_only_flags2 = 0; + + /* NB: Enable the GPR only instructions which are enabled + implicitly by SSE ISAs unless they have been disabled + explicitly. */ + if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags)) + { + if (!TARGET_EXPLICIT_CRC32_P (opts)) + general_regs_only_flags |= OPTION_MASK_ISA_CRC32; + if (!TARGET_EXPLICIT_POPCNT_P (opts)) + general_regs_only_flags |= OPTION_MASK_ISA_POPCNT; + } + if (TARGET_SSE3_P (opts->x_ix86_isa_flags)) + { + if (!TARGET_EXPLICIT_MWAIT_P (opts)) + general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT; + } + /* Disable MMX, SSE and x87 instructions if only general registers are allowed. */ opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; + opts->x_ix86_isa_flags |= general_regs_only_flags; + opts->x_ix86_isa_flags2 |= general_regs_only_flags2; opts->x_ix86_isa_flags_explicit - |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; + |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET + | general_regs_only_flags); opts->x_ix86_isa_flags2_explicit - |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; + |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET + | general_regs_only_flags2); opts->x_target_flags &= ~MASK_80387; } |