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path: root/include/opcode/aarch64.h
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2024-07-18opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat1-1/+2
2024-07-18include: opcodes: aarch64: define new subclassesIndu Bhagat1-1/+31
2024-07-12aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni1-1/+10
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni1-0/+1
2024-07-12aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni1-0/+1
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath1-0/+8
2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo1-0/+3
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo1-0/+3
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo1-1/+5
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas1-0/+8
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni1-3/+1
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni1-1/+1
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni1-1/+1
2024-06-25aarch64: Enable mandatory feature bits for v9.4-A.Srinath Parvathaneni1-1/+2
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti1-0/+11
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti1-6/+31
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-0/+6
2024-06-23aarch64: Enable +cssc for armv8.9-aAndrew Carlotti1-0/+1
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas1-1/+6
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com1-0/+3
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com1-1/+8
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+2
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo1-0/+3
2024-04-17aarch64: Remove asserts from operand qualifier decoders [PR31595]Victor Do Nascimento1-0/+3
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha1-0/+2
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev1-0/+3
2024-02-27aarch64: rename internals related to PAuth feature to use pauth in their nami...Matthieu Longo1-2/+2
2024-01-23aarch64: Include +predres2 in -march=armv8.9-aAndrew Carlotti1-2/+2
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento1-0/+1
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+5
2024-01-15aarch64: rcpc3: Define address operand fields and inserter/extractorsVictor Do Nascimento1-2/+4
2024-01-15aarch64: rcpc3: Create implicit load/store size calc functionVictor Do Nascimento1-0/+3
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento1-0/+2
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-1/+5
2024-01-15aarch64: Remove unused BTI feature bitAndrew Carlotti1-3/+0
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-0/+3
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-1/+4
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-2/+8
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+11
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni1-0/+2
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-1/+4
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha1-0/+15
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni1-0/+1
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento1-0/+2
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento1-0/+1
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento1-1/+6
2024-01-09aarch64: Add support for optional operand pairsVictor Do Nascimento1-1/+11
generated by cgit v1.1 at 2024-08-04 08:48:55 +0000