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AgeCommit message (Expand)AuthorFilesLines
2025-07-12aarch64: Add support for --march=armv9.6-aAlice Carlotti1-0/+10
2025-07-12aarch64: Refactor exclusion of reg names in immediatesAlice Carlotti1-1/+18
2025-07-11aarch64: Support for FEAT_SVE_AES2Ezra Sitorus1-0/+9
2025-07-11aarch64: Support for FEAT_LSUIEzra Sitorus1-0/+2
2025-07-11aarch64: Support for FEAT_PCDPHINTEzra Sitorus1-0/+3
2025-07-10RISC-V: Clarify the imply rule of cNelson Chu1-4/+4
2025-07-09gas d30v_insn plus other non-const pointersAlan Modra1-2/+2
2025-07-08aarch64: Add support for FEAT_SVE2p2 and FEAT_SME2p2Alice Carlotti1-1/+12
2025-06-25aarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+2
2025-06-24RISC-V: Support for unlabeled landing pad PLT generationKito Cheng1-0/+1
2025-06-19aarch64: Support for FEAT_LSFEEzra Sitorus1-2/+7
2025-06-19aarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+6
2025-06-19aarch64: Support for FEAT_CMPBREzra Sitorus1-0/+5
2025-06-19aarch64: Add occmo flag for FEAT_OCCMOEzra Sitorus1-0/+2
2025-06-19aarch64: Support for FEAT_SVE_BFSCALEEzra Sitorus1-0/+5
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball1-0/+4
2025-06-11aarch64: Add definitions for missing architecture bitsYury Khrustalev1-4/+16
2025-06-11kvx gcc-4.5 build fixesAlan Modra1-2/+2
2025-06-09aarch64: Increase the number of feature words to 3Richard Earnshaw1-1/+2
2025-06-09aarch64: use macro trickery to automate feature array size replicationRichard Earnshaw1-36/+87
2025-06-09aarch64: Fix typos in opcode headersYury Khrustalev1-4/+4
2025-05-22RISC-V: Add support for Smcdeleg and Ssccfg extensions.Jiawei1-0/+4
2025-05-16RISC-V: Add zilsd & zclsd supportdysun1-0/+2
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti1-6/+10
2025-05-09RISC-V: Add Privileged Architecture 1.13 CSRs.Jiawei1-0/+4
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu2-0/+69
2025-03-26RISC-V: add Smrnmi 1.0 instruction supportJerry Zhang Jian2-0/+6
2025-03-18RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma2-0/+16
2025-03-03RISC-V: Support ssqosid extension with version 1.0.Kito Cheng1-0/+4
2025-01-17aarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti1-2/+8
2025-01-17RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang2-0/+36
2025-01-17RISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu2-3/+18
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni1-0/+2
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-2/+2
2025-01-10aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti1-1/+1
2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti1-1/+0
2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni1-0/+2
2025-01-06RISC-V: Eliminate redundant instruction macroXiao Zeng1-1/+0
2025-01-01Update year range in copyright notice of binutils filesAlan Modra69-69/+69
2024-12-27LoongArch: Fix resolution of undefined weak hidden/protected symbolsXi Ruoyao1-0/+2
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai1-0/+4
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore3-1790/+0
2024-11-22RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclip...Nelson Chu2-0/+25
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei2-0/+17
2024-11-08aarch64: improve debuggability on array of enumMatthieu Longo1-3/+3
2024-11-08aarch64: change returned type to bool to match semantic of functionsMatthieu Longo1-1/+1
2024-11-08aarch64: make comment clearer about the locationMatthieu Longo1-1/+2
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira1-2/+2
2024-10-10s390: Add arch15 instructionsAndreas Krebbel1-0/+1
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei1-0/+10
generated by cgit v1.1 at 2025-09-17 07:47:10 +0000