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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 12:58:27 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
| commit | 4f2cb9d129f8a5eba81379b70322d013b670045c (patch) | |
| tree | fe78971153fe7f2020d90d45620408a94c7cde9e /include/opcode/aarch64.h | |
| parent | f50b1a3c1f9514efdff6d808b2700eb18ab55630 (diff) | |
| download | binutils-4f2cb9d129f8a5eba81379b70322d013b670045c.zip binutils-4f2cb9d129f8a5eba81379b70322d013b670045c.tar.gz binutils-4f2cb9d129f8a5eba81379b70322d013b670045c.tar.bz2 | |
aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q
as mentioned below, for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html
1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as
predicated instructions and this issue is fixed in this patch by replacing
"SVE2p1_INSNC" with "SVE2p1_INSN" macro.
2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed
by replacing "SVE_Zt" with "SVE_ZtxN".
3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in
this patch.
4) In ld1q/st1q the index in the second argument is optional and if index
is xzr and is skipped in the assembly, the index field is ignored by the
disassembler.
Fixing above mentioned issues helps with following:
1) ld1q and st1q first register operand accepts enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping
sequence of vector registers.
For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
registers are added along with short-form of operands for non-wrapping sequence.
I have added test using following logic:
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes)
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1>
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value)
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value)
ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones)
ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding.
For all the above form of instructions the hyphenated form is preferred for
disassembly if there are more than two registers in the list, and the register
numbers are monotonically increasing in increments of one.
Diffstat (limited to 'include/opcode/aarch64.h')
| -rw-r--r-- | include/opcode/aarch64.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a178e8c..61758c9 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -686,6 +686,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL4, /* SVE [<Xn|SP>, <Xm>, LSL #4]. */ AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */ AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ @@ -861,9 +862,6 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ - AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */ - AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */ - AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */ AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* [<Xn|SP>]{, #<imm>}. */ AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */ |