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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:40:11 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:42 +0000 |
| commit | b33f1bcd152c756c6975f874dbcf58ed3fcc9bdf (patch) | |
| tree | 0961c18129b0a7b98f736dc97029fc9b2f1d748d /include/opcode/aarch64.h | |
| parent | b34104edab8bb399ade7a6c0865af47ff765d576 (diff) | |
| download | binutils-b33f1bcd152c756c6975f874dbcf58ed3fcc9bdf.zip binutils-b33f1bcd152c756c6975f874dbcf58ed3fcc9bdf.tar.gz binutils-b33f1bcd152c756c6975f874dbcf58ed3fcc9bdf.tar.bz2 | |
aarch64: Add SVE2.1 Contiguous load/store instructions.
Hi,
This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'include/opcode/aarch64.h')
| -rw-r--r-- | include/opcode/aarch64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index de161db..189bab5 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -797,6 +797,9 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ + AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */ + AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */ + AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */ }; /* Qualifier constrains an operand. It either specifies a variant of an |