aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-08-13Svadu: Rename HADE to ADUEVed Shanbhogue1-4/+4
2023-07-31rv64_q_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-31rv32_d_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-25Merge pull request #181 from rivosinc/add_smcntrpmf_csrsAndrew Waterman1-0/+4
Add Smcntrpmf CSRs
2023-07-25Merge pull request #182 from ↵Andrew Waterman1-8/+8
nrajovic/fix_vector_mask_register_logical_instructions rv_v: fix for Vector Mask-Register Logical instructions.
2023-07-25rv_v: fix for Vector Mask-Register Logical instructions.Nikola Rajovic1-8/+8
- resolves issue #180
2023-07-24Add Smcntrpmf CSRsAtul Khare1-0/+4
Adds mcyclecfg (0x321), minstrefcfg (0x322), mcyclecfgh (0x721), minstretcfgh (0x722).
2023-07-12Merge branch 'rivosinc-smdeleg_definitions'Andrew Waterman2-0/+14
2023-07-12Add Smcdeleg CSR+constantsAtul Khare2-0/+14
Adds CSR scountinhibit (0x120), MSTATEEN0.CD (bit 56), and siselect range (0x40 - 0x5F).
2023-07-10Merge pull request #178 from rivosinc/smcsrind_sscsrind_csrsAndrew Waterman1-0/+15
Add Smcsrind/Sscsrind CSRs
2023-07-10Add Smcsrind/Sscsrind CSRsAtul Khare1-0/+15
Adds mireg2 (0x352), mireg3 (0x353), mireg4 (0x355), mireg5 (0x356), mireg6 (0x357), sireg2 (0x152), sireg3 (0x153), sireg4 (0x155), sireg5 (0x156), sireg6 (0x157), vsireg2 (0x252), vsireg3 (0x253), vsireg4 (0x255), vsireg5 (0x256), vireg6 (0x257).
2023-05-26Merge pull request #177 from liweiwei90/plct-bf16-devNeel Gala1-2/+2
Update encodings for vfwmaccbf16.vv/vf
2023-05-19Update encodings for vfwmaccbf16.vv/vfWeiwei Li1-2/+2
2023-05-15Merge pull request #176 from ved-rivos/zacasNeel Gala2-0/+3
Add (unratified) Zacas extension
2023-05-13add amocas.q (RV64 only) zacas instructionVed Shanbhogue1-0/+1
2023-05-13add amocas.w/d zacas instructionsVed Shanbhogue1-0/+2
2023-05-02Merge pull request #167 from Lucas-Wye/masterNeel Gala1-2/+28
change decode generation part of chisel
2023-05-02Merge pull request #154 from rivosinc/zvk-vector-cryptoNeel Gala14-8/+218
Support for Zvk, Vector Cryptography Extensions
2023-05-01Support for Zvk, Vector Cryptography ExtensionsEric Gouriou14-8/+218
Add encodings for all instructions in the Zvk extensions: - Zvbb, Vector Bit-manipulation instructions used in Cryptography, - Zvbc, Vector Carryless Multiplication - Zvkg, Vector GCM/GMAC instruction for Cryptography, - Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single Round), - Zvknha, Zvknhb, NIST Suite: Vector SHA-2, - Zvksed, ShangMi Suite: SM4 Block Cipher Instructions - Zvkssh, ShangMi Suite: SM3 Hash Function Instructions Add two "shorthand" extensions: - Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh - Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh Three new fields are listed in constants.py: - 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh), and 5-bit shift constant (vwsll.vi in Zvbb) - 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount in vror.vi. The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the P opcode space. Some encodings conflict with proposed instructions in the P extension (packed SIMD). Zvk and P are exclusive of each other, no implementation will implement both. Conflicting P instructions are marked as pseudo of the Zvk instructions. The encodings match the current documentation of the specification at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>, at Version v0.9.1, 25 April, 2023 (Freeze Candidate). Co-authored-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-04-19Merge pull request #174 from liweiwei90/plct-bf16-devAndrew Waterman3-0/+6
Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.
2023-04-15Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.Weiwei Li3-0/+6
2023-04-07Merge pull request #172 from dramforever/instr_dict_extension_fixNeel Gala1-6/+8
Fix merging of instructions with the same name
2023-04-07Fix merging of instructions with the same namedramforever1-6/+8
Fixes generation of 'extension' field for instr_dict.yaml
2023-03-17use val instead of defLucas-Wye1-5/+1
2023-03-16Merge pull request #170 from ptomsich/ptomsich/zfaPhilipp Tomsich6-0/+33
Add (unratified) Zfa extension
2023-03-17Add (unratified) Zfa extensionPhilipp Tomsich6-0/+33
Zfa adds 'missing' floating-point functionality: - fli.[hsdq]: floating-point load-immediate - fminm/fmaxm.[hsdq]: IEEE 754-2019 minimum and maximum - fround(nx)?.[hsdq]: IEEE 754-2019 roundToIntegral(Exact)? - fcvtmod.w.d: ECMAScript modular float->integer conversion - move instructions for XLEN < FLEN - comparisons that support quiet NaN inputs This adds a surprisingly large number of files, as the instructions added with Zfa depend on context (e.g., .h-variants become available only if Zfh is present).
2023-03-16Merge pull request #169 from riscv/smrnmiAndrew Waterman1-0/+1
Add Smrnmi MNRET instruction
2023-03-16Add Smrnmi MNRET instructionAndrew Waterman1-0/+1
Forgot to add this as part of #168.
2023-03-16Merge pull request #168 from riscv/smrnmiAndrew Waterman2-0/+8
Add Snrmni CSR and field definitions
2023-03-16Add Snrmni CSR and field definitionsAndrew Waterman2-0/+8
2023-03-10change the generation part of chiselLucas-Wye1-2/+32
2023-02-27Merge pull request #166 from eflaner/masterNeel Gala3-3/+0
Removing "grev & grevi" instructions from "unratified/rv*_zbpbo" sub-extensions
2023-02-27Removing all "grev" instances from "zbpbo" sub-extensionsBabu P S3-3/+0
GREV instruction no longer exist in the zbpbo specified by [v0.9.11 spec](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#51-zbpbo)
2023-02-14Move Zawrs to ratified folder (#162)ved-rivos1-0/+0
* Move Zawrs to ratified folder * Move Zawrs to ratified folder
2023-02-06Merge pull request #159 from riscv/revert-158Neel Gala10-329/+322
Revert #158, restoring #147
2023-02-06Revert "Revert "Fix pack instruction in rv_zbpbo""Andrew Waterman1-1/+1
This reverts commit 24cba79065aa975ad91e92c5d59f2e1dafa5ab26.
2023-02-06Revert "Revert "Removing import of csrrs and crrci in rv_zpn""Andrew Waterman1-2/+0
This reverts commit 3485bbcda5509615e4d18708722d67871efb7eaf.
2023-02-06Revert "Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)""Andrew Waterman10-330/+325
This reverts commit 6b5a0648ab6b99507aef3c902afbcd3cd9d90353.
2023-02-05Merge pull request #158 from riscv/revert-p-temporarilyAndrew Waterman10-322/+329
Temporarily revert #147
2023-02-05Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)"Andrew Waterman10-325/+330
This reverts commit 9b0eddd52b9e3c1fbd1dab56ecbaa88747254a2a.
2023-02-05Revert "Removing import of csrrs and crrci in rv_zpn"Andrew Waterman1-0/+2
This reverts commit 2cf6da8f9a370ee5c0012d4ae4f403c3d920d1e8.
2023-02-05Revert "Fix pack instruction in rv_zbpbo"Andrew Waterman1-1/+1
This reverts commit 115e4237407e8c02b945dfb12c086ee57200dd55.
2023-01-31Merge pull request #157 from riscv/work-around-147Andrew Waterman0-0/+0
Temporarily work around #147 breaking Spike
2023-01-31Merge branch 'master' into work-around-147Andrew Waterman12-332/+325
2023-01-31Update encoding.h.out's copyright year.Aaron Durbin1-1/+1
It's a new year. Make the copyright clause reflect 2023.
2023-01-31Add support for SvaduAaron Durbin1-0/+4
The Svadu extension (https://github.com/riscv/riscv-svadu) adds the HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the A/D bits in the PTE. Provide the bit encodings for the HADE support.
2023-01-31updated readmeNeel Gala1-0/+9
2023-01-31rv32_i shift pseudo ops should depend on rv64_i (not rv128_i)Neel Gala1-0/+3
2023-01-31adding pseudo_ops for shift-ops where the mnemonics remain the sameNeel Gala2-3/+6
2023-01-31indenting logs for better readabilityNeel Gala1-2/+2
generated by cgit v1.1 at 2024-10-11 14:05:28 +0000