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| author | Andrew Waterman <andrew@sifive.com> | 2023-03-16 15:06:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-03-16 15:06:42 -0700 |
| commit | da605c83908325289f841486968f6e37fc0f5449 (patch) | |
| tree | 400c0ad727254103ed63188d653a2e0ab0e1094c | |
| parent | ed68c21b025ced3e09bc6ad753947ec8248f89ec (diff) | |
| download | riscv-opcodes-da605c83908325289f841486968f6e37fc0f5449.zip riscv-opcodes-da605c83908325289f841486968f6e37fc0f5449.tar.gz riscv-opcodes-da605c83908325289f841486968f6e37fc0f5449.tar.bz2 | |
Add Snrmni CSR and field definitions
| -rw-r--r-- | constants.py | 4 | ||||
| -rw-r--r-- | encoding.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/constants.py b/constants.py index b211c48..1594677 100644 --- a/constants.py +++ b/constants.py @@ -468,6 +468,10 @@ csrs32 = [ (0x73D, 'mhpmevent29h'), # Sscofpmf (0x73E, 'mhpmevent30h'), # Sscofpmf (0x73F, 'mhpmevent31h'), # Sscofpmf + (0x740, 'mnscratch'), # Smrnmi + (0x741, 'mnepc'), # Smrnmi + (0x742, 'mncause'), # Smrnmi + (0x744, 'mnstatus'), # Smrnmi (0x757, 'mseccfgh'), (0xB80, 'mcycleh'), (0xB82, 'minstreth'), @@ -63,6 +63,10 @@ #define USTATUS_UIE 0x00000001 #define USTATUS_UPIE 0x00000010 +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPP 0x00001800 +#define MNSTATUS_MNPV 0x00000080 + #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) |