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| author | Neel Gala <neelgala@incoresemi.com> | 2023-01-14 13:37:02 +0530 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-31 09:28:07 -0800 |
| commit | ca6217bdb578c1a7cb80e3e0cbba8460dfa899bc (patch) | |
| tree | 88557258073c83829ae29fb0a69376c8ab917ab3 | |
| parent | 97c69d247f8aa30aa82362ce77d36d6602954b29 (diff) | |
| download | riscv-opcodes-ca6217bdb578c1a7cb80e3e0cbba8460dfa899bc.zip riscv-opcodes-ca6217bdb578c1a7cb80e3e0cbba8460dfa899bc.tar.gz riscv-opcodes-ca6217bdb578c1a7cb80e3e0cbba8460dfa899bc.tar.bz2 | |
rv32_i shift pseudo ops should depend on rv64_i (not rv128_i)
| -rw-r--r-- | rv32_i | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -1,3 +1,6 @@ $pseudo_op rv64_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 $pseudo_op rv64_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 $pseudo_op rv64_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::slli slli_rv32 rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli_rv32 rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai_rv32 rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 |