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BranchCommit messageAuthorAge
confprecRemove debug printf in vsetprecQuan Nguyen11 years
cs250don't forget to commit configure after autoconf!Andrew Waterman13 years
cyclehImplement cycleh/instreth CSRs for RV32Andrew Waterman7 years
debug_romClean up/optimize Debug ROM.Tim Newsome6 years
debug_rom_fenceMove fence inside entry_loop.Tim Newsome2 years
device_flagsAllow device flags after --device cmdline argJerry Zhao11 months
dtm_reset_errorReset to "success" instead of "error."Tim Newsome7 years
dts_parsingSupport parsing procs fully from DTSJerry Zhao4 months
dynamicbuild: Dynamically link installed progsJerry Zhao16 months
eos18-bringupfix gcc 4.8 buildYunsup Lee11 years
factor-out-macrosFactor out P extension macros into their own headerAndrew Waterman3 years
fix-bf16Add f64_to_bf16; fix f32_to_bf16Andrew Waterman19 months
force-rttibuild: Include all symbols from extension.o when linking spike's mainJerry Zhao16 months
fp-encodingWIP on FP encodingAndrew Waterman8 years
heterogeneous_mctest_hetero_mcUdit Khanna4 years
hwachav4Merge pull request #11 from arunthomas/readmeAndrew Waterman10 years
increase-stack-sizeSubstantially increase context_t stack sizeAndrew Waterman2 years
itrigger-etrigger-cleanupUse ACTION_DEBUG_MODE instead of 1YenHaoChen24 months
load_reservation_set_sizeadd configurable LR/SC reservation setUdit Khanna4 years
log-commits-fastertmpAndrew Waterman12 months
masterMerge pull request #1848 from riscv-software-src/fix-1846Andrew Waterman5 days
mmio-hackOnly allow SIP.SSIP to be toggled if the interrupt is delegatedAndrew Waterman8 years
mvpAdd vf[ls](|seg)(|st)h and friendsQuan Nguyen11 years
no_progbufPasses smoke tests with --progsize=0Tim Newsome7 years
no_progbuf2Passes smoke tests with --progsize=0Tim Newsome7 years
nolibfdtRemove in-tree libfdt, rely on system-installed libfdtJerry Zhao11 months
p-ext-0.5.2Merge pull request #694 from marcfedorow/p-extChunPing Chung4 years
plctlab-plct-zce-fix2Contain C/Zc*-enable logic entirely within misa_csr_tAndrew Waterman21 months
plic-clint-endianMake clint tolerant of discontiguous hart IDsAndrew Waterman21 months
plic_uart_v1Merge branch 'master' into plic_uart_v1Andrew Waterman2 years
priv-1.10minNum -> minimumNumberAndrew Waterman7 years
private-l1-cachesMake L1 cache models private cachesAndrew Waterman4 years
pte-info-and-delegationAllow delegating misaligned load/store, illegal instructionUdit Khanna5 years
remove-testsRemove generic debug tests.Tim Newsome8 years
rivosinc-etrigger_fix_exception_matchCall stash_privilege more selectivelyAndrew Waterman18 months
rva-profile-supportWIPAndrew Waterman19 months
sifive/rvv0.9-phase2rvv: index register doesn't care about NFChih-Min Chao4 years
simplify-misalignedActually inline load_fast/store_fast for clang/ARMAndrew Waterman2 years
sodorfesvr: decrease DTM idle cycleskritik bhimani5 years
sparse-memAdd int_map and use it to speed up sparse memAndrew Waterman4 years
speed2Predecode common instructionsJerry Zhao5 days
speedup-hackstmpAndrew Waterman22 months
static-linkAdd fesvr; only globally install fesvr headers/libsAndrew Waterman6 years
testEnable precompiled headers when using clangAndrew Waterman3 years
tmpFor NS16550 UART, poll stdin less oftenAndrew Waterman22 months
trigger_prioritySimplify misaligned_load()Tim Newsome2 years
tweak_debug_romDebug ROM: Adjust debug ROM to have fewer icache flushesMegan Wachs7 years
whole-archivebuild: Link spike binaries with --whole-archiveJerry Zhao16 months
 
TagDownloadAuthorAge
dummy-tag-for-ci-storageriscv-isa-sim-dummy-tag-for-ci-storage.zip  riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz  riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2  Andrew Waterman2 years
v1.1.0riscv-isa-sim-1.1.0.zip  riscv-isa-sim-1.1.0.tar.gz  riscv-isa-sim-1.1.0.tar.bz2  Andrew Waterman3 years
v1.0.0riscv-isa-sim-1.0.0.zip  riscv-isa-sim-1.0.0.tar.gz  riscv-isa-sim-1.0.0.tar.bz2  Andrew Waterman6 years
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