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The data value of the function store_slow_path() is meaningful only when
the actually_store=true. Otherwise, the data value is a hollow value of
0, which may result in unintended trigger matching.
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The spec defines that the mcontrol store address/data has a higher
priority over page fault and address misalignment (Debug spec, Table
5.2). Thus, the trigger checking should be before the translation and
alignment checking.
The previous implementation checks the trigger after the translation and
alignment, resulting in incorrect priority. For instance, when page fault
and trigger occur on the same instruction, the previous implementation
will choose to raise the page fault, which contradicts the priority
requirement.
This commit moves the trigger checking before the misaligned checking and
translation. The trigger will fire on the instruction instead of the page
fault in the above case.
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The spec defines the mcontrol load address has a higher priority over
page fault and address misaligned (Debug spec, Table 5.2). Thus, the
trigger checking should be before the translation and alignment
checking.
The previous implementation checks the trigger after the translation
and alignment, resulting in incorrect priority. For instance, when page
fault and trigger occur on the same instruction, the previous
implementation will choose to raise the page fault, which contradicts
the priority requirement.
This commit adds an address-only trigger checking before the misaligned
checking and translation. The trigger will fire on the instruction
instead of the page fault in the above case.
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The mcontrol trigger can select either address or data for checking. The
The selection decides the priority of the trigger. For instance, the
address trigger has a higher priority over the page fault, and the page
fault has a higher priority over the data trigger.
The previous implementation only has the checking functions for data
trigger, which results in incorrect priority of address trigger.
This commit adds a has_data argument to indicate address trigger and the
priority of the trigger.
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See #990.
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tablewalks
Fix issue #990.
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Didn't want to make change in previous commit to isolate the change.
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start of AMO.
This includes skipping store in store_slow_path.
Is okay to skip the mmio_store part too, since the access_fault for mmio_failure will be caught on the actual store.
The ordering for the mmio_access fault is irrelevant since it will occur after the TW faults, and load faults are converted to store faults.
Will catch any faults from the access but won't perform a store.
Since store permissions can only be granted if read permissions exist,
any store faults will occur before or at the same time as a load fault.
Thus this store permissions check is sufficient for properly catching the faults in an Amo access TW.
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Will be used to check store attributes without actually performing the store.
Needed to AMO bug fix.
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Based on this statement from priv spec 5.5.1 (regarding Sv39x4):
"Address bits 63:41 must all be zeros, or else a guest-page-fault
exception occurs."
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This was much more complicated than the others because of the
mstatus.TVM and hstatus.VTVM bits, and because of the special
WARL-ness of satp that doesn't apply to vsatp.
It appears (based on reading the code) that the commitlog for these
two was problematic. CSRW to satp when V=1 was reporting a write to
satp instead of vsatp which was actually written. Also a CSRW to
vsatp looks like it was not being logged at all. Both problems
should be fixed now.
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Spike does not support dynamic xlen today, but if it should in the
future, this will help identify all the code that needs to be updated.
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Step 5 of plan in csrs.h.
This changes the commitlog to properly report when the architectural
`vsstatus` register is written, e.g. by `csrw sstatus` in VS-mode.
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Step 3 of plan described in csrs.h.
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Part of step 2 of plan described in csrs.h.
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Part of step 2 of plan described in csrs.h.
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Makes a mess out of the tracing though, because of how every toggle of
the VBit swaps mstatus and vsstatus.
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We've already checked just a few lines up that proc is defined.
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This was the last place outside of the csr_t hierarchy that pmpcfg was
being accessed.
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Since that's what it was returning anyway.
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Since match4() checks this now.
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To simplify calling code.
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This will enable further restructuring of these loops in mmu.cc in the
next commits.
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See discussion at
https://github.com/riscv/riscv-isa-sim/commit/9cfc3e7fef7b29f6b53879d7c91c35459d9b493d#r55593451
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Continuation of 80be4e21c3af7fe2966788ce538d3e3c3b0d60e3
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into daniellustig-nonleaf_dau
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...and hence should trigger page faults
Thanks to @pdonahue-ventana for pointing this out:
https://github.com/riscv/riscv-tests/issues/352
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When V=1, vsstatus.MXR applies to the first stage of translation,
and mstatus.MXR applies to both.
mstatus.SUM doesn't apply when V=1, but vsstatus.SUM does.
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It should require X permissions, rather than (R || X).
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The previous scheme flushed the TLB before and after HLV/HSV. I think
this was slightly wrong in the case of a debug trigger match: because
the TLB gets refilled before the trigger exception gets thrown, we might
not have reached the second TLB flush, so the entry could linger.
Instead of flushing, simply don't access the TLB and don't refill the
TLB for these instructions. Other than the trigger exception case,
the effect is the same: we'll perform a full table walk and we won't
cache the result.
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* Priv virtual memory updates
* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set
* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)
* Add Svinval instructions
Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...
If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.
* Svinval: use #include rather than copying code
..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions
Thanks to @aswaterman for the suggestion
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The wrong instruction might've been fetched when the PC was on the same
page as a load or store used within the MPRV sequence.
Fix by not using TLB within MPRV sequences.
Resolves #746
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* Don't make MPRV load/store virtual if MPV=1, MPP=3
* Use PRV_M instead of the value "3"
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We cannot blindly use proc variable in MMU emulation because external
debug emulation instantiates MMU with proc=NULL.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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