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| author | Tim Newsome <tim@sifive.com> | 2022-03-15 08:14:50 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:38:53 -0700 |
| commit | a2a2587426e57f6207d5389620e9109bc0f82e6b (patch) | |
| tree | 94ac06e2e8797bf0a8ef3b4c08175450f37acd83 /riscv/mmu.cc | |
| parent | 273fa05167c873e2cc92862ddbb52b10806f439a (diff) | |
| download | riscv-isa-sim-a2a2587426e57f6207d5389620e9109bc0f82e6b.zip riscv-isa-sim-a2a2587426e57f6207d5389620e9109bc0f82e6b.tar.gz riscv-isa-sim-a2a2587426e57f6207d5389620e9109bc0f82e6b.tar.bz2 | |
trigger_operation_t -> triggers::operation_t
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 275383d..fd8a320 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -155,7 +155,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate if (!matched_trigger) { reg_t data = reg_from_bytes(len, bytes); - matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); + matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, data); if (matched_trigger) throw *matched_trigger; } @@ -167,7 +167,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_ if (!matched_trigger) { reg_t data = reg_from_bytes(len, bytes); - matched_trigger = trigger_exception(OPERATION_STORE, addr, data); + matched_trigger = trigger_exception(triggers::OPERATION_STORE, addr, data); if (matched_trigger) throw *matched_trigger; } |