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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-03-08 22:20:32 -0800 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2021-09-08 07:59:02 -0700 |
commit | ba6f0dc65c14780683f2248274a3395dc7df02fa (patch) | |
tree | c1dc74a47bf81d0de8182f05bc8ad6a3b2bd45e6 /riscv/mmu.cc | |
parent | 96aed2f5745e2effc173dc6cd2d2d24fa0d49c2f (diff) | |
download | riscv-isa-sim-ba6f0dc65c14780683f2248274a3395dc7df02fa.zip riscv-isa-sim-ba6f0dc65c14780683f2248274a3395dc7df02fa.tar.gz riscv-isa-sim-ba6f0dc65c14780683f2248274a3395dc7df02fa.tar.bz2 |
Convert hstatus to csr_t family
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 0d6509a..b880739 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -64,7 +64,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f } if (xlate_flags & RISCV_XLATE_VIRT) { virt = true; - mode = get_field(proc->state.hstatus, HSTATUS_SPVP); + mode = get_field(proc->state.hstatus->read(), HSTATUS_SPVP); } } |