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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-03-04 15:22:35 -0800 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2021-09-08 07:59:02 -0700 |
commit | 44c83df675358b8aa8473710613d5673471f362e (patch) | |
tree | dba4d316b22d808bcc89302f0aacc95eb17bfdbc /riscv/mmu.cc | |
parent | b0edd7139f678a35fe0053676a02b0fa112e95d1 (diff) | |
download | riscv-isa-sim-44c83df675358b8aa8473710613d5673471f362e.zip riscv-isa-sim-44c83df675358b8aa8473710613d5673471f362e.tar.gz riscv-isa-sim-44c83df675358b8aa8473710613d5673471f362e.tar.bz2 |
Convert mmu_t::walk to use sstatus
Part of step 2 of plan described in csrs.h.
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 3bfb630..c214884 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -347,10 +347,10 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx return s2xlate(addr, addr & ((reg_t(2) << (proc->xlen-1))-1), type, type, virt, hlvx) & ~page_mask; // zero-extend from xlen bool s_mode = mode == PRV_S; - reg_t arch_vsstatus = proc->state.v ? proc->state.mstatus : proc->state.vsstatus->read(); - reg_t arch_mstatus = proc->state.v ? proc->state.vsstatus->read() : proc->state.mstatus; - bool sum = (virt ? arch_vsstatus : arch_mstatus) & MSTATUS_SUM; - bool mxr = (arch_mstatus | (virt ? arch_vsstatus : 0)) & MSTATUS_MXR; + reg_t arch_vsstatus = proc->state.v ? proc->state.sstatus->read() : proc->state.vsstatus->read(); + reg_t arch_sstatus = proc->state.v ? proc->state.vsstatus->read() : proc->state.sstatus->read(); + bool sum = (virt ? arch_vsstatus : arch_sstatus) & MSTATUS_SUM; + bool mxr = (arch_sstatus | (virt ? arch_vsstatus : 0)) & MSTATUS_MXR; // verify bits xlen-1:va_bits-1 are all equal int va_bits = PGSHIFT + vm.levels * vm.idxbits; |