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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-01 09:51:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2021-09-08 07:59:02 -0700 |
| commit | b0edd7139f678a35fe0053676a02b0fa112e95d1 (patch) | |
| tree | bffe5158bc2a29045ace321e191c2bcf9b8a2ee7 /riscv/mmu.cc | |
| parent | 58f0f46c10c3c3e2c39bee2eae04570b58204d07 (diff) | |
| download | riscv-isa-sim-b0edd7139f678a35fe0053676a02b0fa112e95d1.zip riscv-isa-sim-b0edd7139f678a35fe0053676a02b0fa112e95d1.tar.gz riscv-isa-sim-b0edd7139f678a35fe0053676a02b0fa112e95d1.tar.bz2 | |
Convert s2xlate() to use sstatus
Part of step 2 of plan described in csrs.h.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index b935f41..3bfb630 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -267,8 +267,8 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty if (vm.levels == 0) return gpa; - reg_t arch_mstatus = proc->state.v ? proc->state.vsstatus->read() : proc->state.mstatus; - bool mxr = arch_mstatus & MSTATUS_MXR; + reg_t arch_sstatus = proc->state.v ? proc->state.vsstatus->read() : proc->state.sstatus->read(); + bool mxr = arch_sstatus & MSTATUS_MXR; reg_t base = vm.ptbase; for (int i = vm.levels - 1; i >= 0; i--) { |