| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-10-19 | Fix imprecise exception on LR to MMIO space | Andrew Waterman | 1 | -3/+1 |
| 2021-06-12 | Revert the redundant check for lr instruction (#728) | sven | 1 | -1/+1 |
| 2021-05-25 | Add alignment check for lr instruction (#713) | sven | 1 | -1/+1 |
| 2020-11-11 | Make LR properly take misaligned exception | Scott Johnson | 1 | -1/+1 |
| 2020-03-23 | Don't acquire load reservation in the event of a fault | Andrew Waterman | 1 | -1/+2 |
| 2018-07-10 | Refactor and fix LR/SC implementation (#217) | Andrew Waterman | 1 | -1/+1 |
| 2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -0/+1 |
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 |
| 2013-08-11 | Instructions are no longer member functions | Andrew Waterman | 1 | -1/+2 |
| 2013-03-29 | add load-reserved/store-conditional instructions | Andrew Waterman | 1 | -0/+1 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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