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| author | sven <zhongcy93@163.com> | 2021-05-25 18:05:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-25 03:05:04 -0700 |
| commit | e2691f0a53e083b7495b6aa50634ac22d464369b (patch) | |
| tree | 09b177f48ea75528345668e8dea8e6d8720cc7ba /riscv/insns/lr_w.h | |
| parent | 46300119843e117dee006008d07129f0e83fd23b (diff) | |
| download | riscv-isa-sim-e2691f0a53e083b7495b6aa50634ac22d464369b.zip riscv-isa-sim-e2691f0a53e083b7495b6aa50634ac22d464369b.tar.gz riscv-isa-sim-e2691f0a53e083b7495b6aa50634ac22d464369b.tar.bz2 | |
Add alignment check for lr instruction (#713)
Co-authored-by: zhongcy <zhongcy93@gmail.com>
Diffstat (limited to 'riscv/insns/lr_w.h')
| -rw-r--r-- | riscv/insns/lr_w.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h index 185be53..6083214 100644 --- a/riscv/insns/lr_w.h +++ b/riscv/insns/lr_w.h @@ -1,4 +1,4 @@ require_extension('A'); auto res = MMU.load_int32(RS1, true); -MMU.acquire_load_reservation(RS1); +MMU.acquire_load_reservation(RS1, 4); WRITE_RD(res); |