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author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-20 14:18:46 -0700 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-21 10:29:19 -0700 |
commit | 24d5693930b1e5657971941a64cb3bd9165e76d4 (patch) | |
tree | 01e5ebaeffcb807bffb76a3322d62501ca2f1694 | |
parent | a3a626b924ded1a0535334a65464f5ee3580d0a2 (diff) | |
download | riscv-isa-sim-24d5693930b1e5657971941a64cb3bd9165e76d4.zip riscv-isa-sim-24d5693930b1e5657971941a64cb3bd9165e76d4.tar.gz riscv-isa-sim-24d5693930b1e5657971941a64cb3bd9165e76d4.tar.bz2 |
Relax has_fs dependency on misa.v
isa_parser should already require any Zvef or Zved extensions
imply F/D
-rw-r--r-- | riscv/csrs.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 8d7737f..ad5ae08 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -411,8 +411,7 @@ base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr): reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { // If a configuration has FS bits, they will always be accessible no // matter the state of misa. - const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F') - || proc->extension_enabled('V')) && !proc->extension_enabled(EXT_ZFINX); + const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F')) && !proc->extension_enabled(EXT_ZFINX); const bool has_vs = proc->extension_enabled('V'); return 0 | (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0) |