Merge branch 'NXP-zilsd'

11 files changed, 83 insertions, 17 deletions

diff --git a/README.md b/README.md
index c6f8484..51af8bc 100644
--- a/README.md
+++ b/README.md
@@ -61,6 +61,8 @@ Spike supports the following RISC-V ISA features:
   - Zvkt  extension, v1.0
   - Zvkn, Zvknc, Zvkng extension, v1.0
   - Zvks, Zvksc, Zvksg extension, v1.0 
+  - Zilsd extension, v0.9.0
+  - Zcmlsd extension, v0.9.0
 
 Versioning and APIs
 -------------------
diff --git a/disasm/disasm.cc b/disasm/disasm.cc
index 7c07ec3..5c0e9e0 100644
--- a/disasm/disasm.cc
+++ b/disasm/disasm.cc
@@ -1391,11 +1391,14 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
     if (isa->get_max_xlen() == 32) {
       DISASM_INSN("c.jal", c_jal, 0, {&rvc_jump_target});
     } else {
+      DISASM_INSN("c.addiw", c_addiw, 0, {&xrd, &rvc_imm});
+    }
+
+    if (isa->get_max_xlen() == 64 || isa->extension_enabled(EXT_ZCMLSD)) {
       DISASM_INSN("c.ld", c_ld, 0, {&rvc_rs2s, &rvc_ld_address});
       DISASM_INSN("c.ldsp", c_ldsp, 0, {&xrd, &rvc_ldsp_address});
       DISASM_INSN("c.sd", c_sd, 0, {&rvc_rs2s, &rvc_ld_address});
       DISASM_INSN("c.sdsp", c_sdsp, 0, {&rvc_rs2, &rvc_sdsp_address});
-      DISASM_INSN("c.addiw", c_addiw, 0, {&xrd, &rvc_imm});
     }
   }
 
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc
index ee57a51..7d3d002 100644
--- a/disasm/isa_parser.cc
+++ b/disasm/isa_parser.cc
@@ -239,6 +239,12 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZICOND] = true;
     } else if (ext_str == "zihpm") {
       extension_table[EXT_ZIHPM] = true;
+    } else if (ext_str == "zilsd") {
+      if (max_xlen != 32)
+        bad_isa_string(str, "'Zilsd' requires RV32");
+      extension_table[EXT_ZILSD] = true;
+    } else if (ext_str == "zcmlsd") {
+      extension_table[EXT_ZCMLSD] = true;
     } else if (ext_str == "zvbb") {
       extension_table[EXT_ZVBB] = true;
     } else if (ext_str == "zvbc") {
@@ -324,6 +330,14 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
     bad_isa_string(str, ("can't parse: " + std::string(p)).c_str());
   }
 
+  if (extension_table[EXT_ZCMLSD] && extension_table[EXT_ZCF]) {
+    bad_isa_string(str, "'Zcmlsd' extension conflicts with 'Zcf' extensions");
+  }
+
+  if (extension_table[EXT_ZCMLSD] && (!extension_table[EXT_ZCA] || !extension_table[EXT_ZILSD])) {
+    bad_isa_string(str, "'Zcmlsd' extension requires 'Zca' and 'Zilsd' extensions");
+  }
+
   if (extension_table[EXT_ZFBFMIN] && !extension_table['F']) {
     bad_isa_string(str, "'Zfbfmin' extension requires 'F' extension");
   }
diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h
index bd871fa..7365a86 100644
--- a/riscv/decode_macros.h
+++ b/riscv/decode_macros.h
@@ -42,6 +42,15 @@
   })
 #define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0};
 
+/* the value parameter needs to be evaluated before writing to the registers */
+#define WRITE_REG_PAIR(reg, value) \
+  if (reg != 0) { \
+    require((reg) % 2 == 0); \
+    uint64_t val = (value); \
+    WRITE_REG(reg, sext32(val)); \
+    WRITE_REG((reg) + 1, (sreg_t(val)) >> 32); \
+  }
+
 // RVC macros
 #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
@@ -69,13 +78,15 @@
 #define RS1_PAIR READ_REG_PAIR(insn.rs1())
 #define RS2_PAIR READ_REG_PAIR(insn.rs2())
 #define RD_PAIR READ_REG_PAIR(insn.rd())
+#define WRITE_RD_PAIR(value) WRITE_REG_PAIR(insn.rd(), value)
 
-#define WRITE_RD_PAIR(value) \
-  if (insn.rd() != 0) { \
-    require(insn.rd() % 2 == 0); \
-    WRITE_REG(insn.rd(), sext32(value)); \
-    WRITE_REG(insn.rd() + 1, (sreg_t(value)) >> 32); \
-  }
+// Zilsd macros
+#define WRITE_RD_D(value) (xlen == 32 ? WRITE_RD_PAIR(value) : WRITE_RD(value))
+
+// Zcmlsd macros
+#define WRITE_RVC_RS2S_PAIR(value) WRITE_REG_PAIR(insn.rvc_rs2s(), value)
+#define RVC_RS2S_PAIR READ_REG_PAIR(insn.rvc_rs2s())
+#define RVC_RS2_PAIR READ_REG_PAIR(insn.rvc_rs2())
 
 // FPU macros
 #define READ_ZDINX_REG(reg) (xlen == 32 ? f64(READ_REG_PAIR(reg)) : f64(STATE.XPR[reg] & (uint64_t)-1))
@@ -122,8 +133,7 @@ do { \
 do { \
   if (p->extension_enabled(EXT_ZFINX)) { \
     if (xlen == 32) { \
-      uint64_t val = (value).v; \
-      WRITE_RD_PAIR(val); \
+      WRITE_RD_PAIR((value).v); \
     } else { \
       WRITE_REG(insn.rd(), (value).v); \
     } \
diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h
index 988ea98..18e0d5e 100644
--- a/riscv/insns/c_ld.h
+++ b/riscv/insns/c_ld.h
@@ -1,2 +1,8 @@
 require_extension(EXT_ZCA);
-WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));
+require((xlen == 64) || p->extension_enabled(EXT_ZCMLSD));
+
+if (xlen == 32) {
+  WRITE_RVC_RS2S_PAIR(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));
+} else {
+  WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));
+}
diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h
index f196040..d8c8ec8 100644
--- a/riscv/insns/c_ldsp.h
+++ b/riscv/insns/c_ldsp.h
@@ -1,3 +1,9 @@
 require_extension(EXT_ZCA);
+require((xlen == 64) || p->extension_enabled(EXT_ZCMLSD));
 require(insn.rvc_rd() != 0);
-WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
+
+if (xlen == 32) {
+  WRITE_RD_PAIR(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
+} else {
+  WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
+}
diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h
index ff8f77d..dba9b07 100644
--- a/riscv/insns/c_sd.h
+++ b/riscv/insns/c_sd.h
@@ -1,2 +1,8 @@
 require_extension(EXT_ZCA);
-MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
+require((xlen == 64) || p->extension_enabled(EXT_ZCMLSD));
+
+if (xlen == 32) {
+  MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S_PAIR);
+} else {
+  MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
+}
diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
index f7b8a28..e95aefa 100644
--- a/riscv/insns/c_sdsp.h
+++ b/riscv/insns/c_sdsp.h
@@ -1,2 +1,8 @@
 require_extension(EXT_ZCA);
-MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
+require((xlen == 64) || p->extension_enabled(EXT_ZCMLSD));
+
+if (xlen == 32) {
+  MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2_PAIR);
+} else {
+  MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
+}
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 3dea301..cb0399b 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,8 @@
-require_rv64;
-WRITE_RD(MMU.load<int64_t>(RS1 + insn.i_imm()));
+require((xlen == 64) || p->extension_enabled(EXT_ZILSD));
+
+if (xlen == 32) {
+  WRITE_RD_PAIR(MMU.load<int64_t>(RS1 + insn.i_imm()));
+} else {
+  WRITE_RD(MMU.load<int64_t>(RS1 + insn.i_imm()));
+}
+
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 5c9dd4e..c80f137 100644
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,7 @@
-require_rv64;
-MMU.store<uint64_t>(RS1 + insn.s_imm(), RS2);
+require((xlen == 64) || p->extension_enabled(EXT_ZILSD));
+
+if (xlen == 32) {
+  MMU.store<uint64_t>(RS1 + insn.s_imm(), RS2_PAIR);
+} else {
+  MMU.store<uint64_t>(RS1 + insn.s_imm(), RS2);
+}
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
index 65c34fd..ae9ed94 100644
--- a/riscv/isa_parser.h
+++ b/riscv/isa_parser.h
@@ -23,6 +23,7 @@ typedef enum {
   EXT_ZCB,
   EXT_ZCD,
   EXT_ZCF,
+  EXT_ZCMLSD,
   EXT_ZCMP,
   EXT_ZCMT,
   EXT_ZKND,
@@ -53,6 +54,7 @@ typedef enum {
   EXT_ZICNTR,
   EXT_ZICOND,
   EXT_ZIHPM,
+  EXT_ZILSD,
   EXT_ZVBB,
   EXT_ZVBC,
   EXT_ZVFBFMIN,