rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-14	rvv: dont't explicit throw exception	Chih-Min Chao	1	-1/+1
2020-05-14	rvv: fix the fractional lmul	Dave.Wen	2	-8/+19
2020-05-13	rvv: wrong operation to the fractional LMUL bit	Dave.Wen	1	-1/+1
2020-05-13	rvv: amo: fix wrong index eew	Chih-Min Chao	27	-27/+27
2020-05-13	rvv: change to 0.9amo	Chih-Min Chao	48	-83/+218
2020-05-13	rvv: amo pre-0.9	Chih-Min Chao	13	-0/+89
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	4	-10/+20
2020-05-13	vtype: fix the vta and vma functions and debugging display	Dave.Wen	3	-3/+6
2020-05-13	eew: add eew	Dave.Wen	1	-8/+17
2020-05-13	eew: fix the eew=0 case	Dave.Wen	2	-13/+18
2020-05-12	rvv: add ext opcode	Chih-Min Chao	1	-0/+18
2020-05-12	rvv: op: change vfunary0 and funary1 func6 field	Chih-Min Chao	1	-47/+47
2020-05-12	rvv: ldst: add missng check for VI_LD	Chih-Min Chao	1	-2/+1
2020-05-11	rvv: change to 0.9 ldst	Chih-Min Chao	78	-451/+638
2020-05-07	rvv: add eew and lmul for vle/vse/vleff	Dave.Wen	4	-7/+39
2020-05-06	fractional_lmul: update the vtype register and alos remove the useless reg_mask	Dave.Wen	1	-1/+3
2020-05-04	zfh: implementation all instructions	Chih-Min Chao	37	-0/+206
2020-05-04	zfh: op: add scalar opcode	Chih-Min Chao	1	-0/+108
2020-04-29	zfh: zfh require F extension support	Chih-Min Chao	1	-0/+3
2020-04-27	rvv: align VCSR with upstream	Chih-Min Chao	2	-15/+13
2020-04-27	parse: refine error format reporting	Chih-Min Chao	1	-10/+24
2020-04-27	rvv: commitlog: fix comparision dst information	Chih-Min Chao	3	-6/+9
2020-04-24	rvv: commitlog: fix missing informaiton for slide1	Chih-Min Chao	4	-12/+12
2020-04-24	rvv: commitlog: fix dst information for int comparison	Chih-Min Chao	1	-20/+40
2020-04-23	build: quota string with [] to avoid part of string missing	Chih-Min Chao	1	-1/+1
2020-04-23	rvv: fix vfncvt.xu.f.w for fp16	Chih-Min Chao	1	-1/+1
2020-04-23	rvv: aad fp16 support for vfwxxx.[wv]v	Chih-Min Chao	10	-8/+47
2020-04-22	rvv: fix segment load/store nf checking	Chih-Min Chao	2	-9/+11
2020-04-21	rvv: fix vfmv for fp16	Chih-Min Chao	3	-13/+36
2020-04-21	rvv: fix vfmerge.vfm for fp16	Chih-Min Chao	1	-2/+15
2020-04-21	rvv: fix vfslide for fp16	Chih-Min Chao	2	-0/+16
2020-04-21	rvv: fix floating comparison for fp16	Chih-Min Chao	10	-11/+49
2020-04-21	rvv: allow fp16	Chih-Min Chao	1	-1/+2
2020-04-20	rvv: refine vfncvt case for f32_to_[u]i16 cases	Chih-Min Chao	3	-6/+3
2020-04-20	rvv: fix f16_to_[u]i16 conversion	Chih-Min Chao	4	-8/+4
2020-04-20	rvv: remove debug message	Chih-Min Chao	1	-1/+0
2020-04-19	rvv: fix vfwredsum checking rule	Chih-Min Chao	1	-1/+3
2020-04-16	rvv: fix rtz cvt	Chih-Min Chao	13	-51/+47
2020-04-15	rvv: add widen conversion instructions	Chih-Min Chao	7	-51/+53
2020-04-15	rvv: add narrow conversion instrucitons	Chih-Min Chao	7	-42/+71
2020-04-15	rvv: add normal and widen reduction instructions	Chih-Min Chao	7	-27/+78
2020-04-15	rvv: add vmfxx f16 compare instructions	Chih-Min Chao	11	-2/+39
2020-04-15	rvv: add .vf fp16 instructions	Chih-Min Chao	25	-3/+85
2020-04-15	rvv: add .vv fp16 instructions	Chih-Min Chao	22	-2/+72
2020-04-15	rvv: WIDE_END loop macro	Chih-Min Chao	1	-9/+4
2020-04-15	fp16: add helper macro	Chih-Min Chao	1	-0/+8
2020-04-14	parser: extend --isa to support extended extension	Chih-Min Chao	2	-18/+55
2020-04-14	rvv: leave only SEW-bit segment store	Chih-Min Chao	17	-153/+53
2020-04-14	rvv: leave only sew-wise segment load	Chih-Min Chao	29	-73/+76
2020-04-14	rvv: add vfslide1[down\|up].vf and refine checking rule	Chih-Min Chao	11	-27/+79