rvv: leave only sew-wise segment load

new features in spec 0.9

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

29 files changed, 76 insertions, 73 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 1e03b59..36fea27 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1518,13 +1518,15 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   } \
   P.VU.vstart = 0; 
 
-#define VI_LD_COMMON(stride, offset, ld_width, elt_byte) \
-  const reg_t nf = insn.v_nf() + 1; \
+#define VI_LD_COMMON(stride, offset, ld_width, elt_byte, is_seg) \
+  const reg_t nf = is_seg ? insn.v_nf() + 1 : 1; \
   const reg_t vl = P.VU.vl; \
   const reg_t baseAddr = RS1; \
   const reg_t vd = insn.rd(); \
   require((nf * P.VU.vlmul) <= (NVPR / 4) && \
           (vd + nf * P.VU.vlmul) <= NVPR); \
+  if (!is_seg) \
+    require(nf == 1); \
   const reg_t vlmul = P.VU.vlmul; \
   for (reg_t i = 0; i < vl; ++i) { \
     VI_ELEMENT_SKIP(i); \
@@ -1549,13 +1551,13 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   } \
   P.VU.vstart = 0;
 
-#define VI_LD(stride, offset, ld_width, elt_byte) \
+#define VI_LD(stride, offset, ld_width, elt_byte, is_seg) \
   VI_CHECK_SXX; \
-  VI_LD_COMMON(stride, offset, ld_width, elt_byte)
+  VI_LD_COMMON(stride, offset, ld_width, elt_byte, is_seg)
 
-#define VI_LD_INDEX(stride, offset, ld_width, elt_byte) \
+#define VI_LD_INDEX(stride, offset, ld_width, elt_byte, is_seg) \
   VI_CHECK_LD_INDEX; \
-  VI_LD_COMMON(stride, offset, ld_width, elt_byte) \
+  VI_LD_COMMON(stride, offset, ld_width, elt_byte, is_seg) \
   if (nf >= 2) \
     require(!is_overlapped(vd, nf, insn.rs2(), 1));
 
@@ -1567,10 +1569,12 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   VI_CHECK_ST_INDEX; \
   VI_ST_COMMON(stride, offset, st_width, elt_byte) \
 
-#define VI_LDST_FF(itype, tsew) \
+#define VI_LDST_FF(itype, tsew, is_seg) \
   require(p->VU.vsew >= e##tsew && p->VU.vsew <= e64); \
-  const reg_t nf = insn.v_nf() + 1; \
+  const reg_t nf = is_seg ? insn.v_nf() + 1 : 1; \
   require((nf * P.VU.vlmul) <= (NVPR / 4)); \
+  if (!is_seg) \
+    require(nf == 1); \
   VI_CHECK_SXX; \
   const reg_t sew = p->VU.vsew; \
   const reg_t vl = p->VU.vl; \
diff --git a/riscv/insns/vlb_v.h b/riscv/insns/vlb_v.h
index a83587d..f5aaa6e 100644
--- a/riscv/insns/vlb_v.h
+++ b/riscv/insns/vlb_v.h
@@ -1,3 +1,3 @@
-// vlb.v and vlseg[2-8]b.v
+// vlb.v
 require(P.VU.vsew >= e8);
-VI_LD(0, i * nf + fn, int8, 1);
+VI_LD(0, i * nf + fn, int8, 1, false);
diff --git a/riscv/insns/vlbff_v.h b/riscv/insns/vlbff_v.h
index 6517315..06419dd 100644
--- a/riscv/insns/vlbff_v.h
+++ b/riscv/insns/vlbff_v.h
@@ -1,2 +1,2 @@
-// vlbff.v and vlseg[2-8]bff.v
-VI_LDST_FF(int, 8);
+// vlbff.v
+VI_LDST_FF(int, 8, false);
diff --git a/riscv/insns/vlbu_v.h b/riscv/insns/vlbu_v.h
index c1e3ea7..8f29679 100644
--- a/riscv/insns/vlbu_v.h
+++ b/riscv/insns/vlbu_v.h
@@ -1,3 +1,3 @@
-// vlbu.v and vlseg[2-8]bu.v
+// vlbu.v
 require(P.VU.vsew >= e8);
-VI_LD(0, i * nf + fn, uint8, 1);
+VI_LD(0, i + fn, uint8, 1, false);
diff --git a/riscv/insns/vlbuff_v.h b/riscv/insns/vlbuff_v.h
index 53a0685..dbe3130 100644
--- a/riscv/insns/vlbuff_v.h
+++ b/riscv/insns/vlbuff_v.h
@@ -1,2 +1,2 @@
-// vlbuff.v and vlseg[2-8]buff.v
-VI_LDST_FF(uint, 8);
+// vlbuff.v
+VI_LDST_FF(uint, 8, false);
diff --git a/riscv/insns/vle_v.h b/riscv/insns/vle_v.h
index 67261cc..b733a3c 100644
--- a/riscv/insns/vle_v.h
+++ b/riscv/insns/vle_v.h
@@ -2,12 +2,12 @@
 reg_t sew = P.VU.vsew;
 
 if (sew == e8) {
-  VI_LD(0, (i * nf + fn), int8, 1);
+  VI_LD(0, (i * nf + fn), int8,  1, true);
 } else if (sew == e16) {
-  VI_LD(0, (i * nf + fn), int16, 2);
+  VI_LD(0, (i * nf + fn), int16, 2, true);
 } else if (sew == e32) {
-  VI_LD(0, (i * nf + fn), int32, 4);
+  VI_LD(0, (i * nf + fn), int32, 4, true);
 } else if (sew == e64) {
-  VI_LD(0, (i * nf + fn), int64, 8);
+  VI_LD(0, (i * nf + fn), int64, 8, true);
 }
 
diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h
index 745c724..09d0e58 100644
--- a/riscv/insns/vleff_v.h
+++ b/riscv/insns/vleff_v.h
@@ -1,12 +1,12 @@
-// vleff.v
+// vleff.v and vleseg[2-8]ff.v
 reg_t sew = P.VU.vsew;
 
 if (sew == e8) {
-  VI_LDST_FF(int, 8);
+  VI_LDST_FF(int,  8, true);
 } else if (sew == e16) {
-  VI_LDST_FF(int, 16);
+  VI_LDST_FF(int, 16, true);
 } else if (sew == e32) {
-  VI_LDST_FF(int, 32);
+  VI_LDST_FF(int, 32, true);
 } else if (sew == e64) {
-  VI_LDST_FF(int, 64);
+  VI_LDST_FF(int, 64, true);
 }
diff --git a/riscv/insns/vlh_v.h b/riscv/insns/vlh_v.h
index d976693..3bdfd6e 100644
--- a/riscv/insns/vlh_v.h
+++ b/riscv/insns/vlh_v.h
@@ -1,3 +1,3 @@
-// vlh.v and vlseg[2-8]h.v
+// vlh.v
 require(P.VU.vsew >= e16);
-VI_LD(0, i * nf + fn, int16, 2);
+VI_LD(0, i * nf + fn, int16, 2, false);
diff --git a/riscv/insns/vlhff_v.h b/riscv/insns/vlhff_v.h
index c4c2d8e..c003301 100644
--- a/riscv/insns/vlhff_v.h
+++ b/riscv/insns/vlhff_v.h
@@ -1,2 +1,2 @@
-// vlh.v and vlseg[2-8]hff.v
-VI_LDST_FF(int, 16);
+// vlh.v
+VI_LDST_FF(int, 16, false);
diff --git a/riscv/insns/vlhu_v.h b/riscv/insns/vlhu_v.h
index 5b936dd..98f3280 100644
--- a/riscv/insns/vlhu_v.h
+++ b/riscv/insns/vlhu_v.h
@@ -1,3 +1,3 @@
-// vlhu.v and vlseg[2-8]hu.v
+// vlhu.v
 require(P.VU.vsew >= e16);
-VI_LD(0, i * nf + fn, uint16, 2);
+VI_LD(0, i * nf + fn, uint16, 2, false);
diff --git a/riscv/insns/vlhuff_v.h b/riscv/insns/vlhuff_v.h
index f23f82d..bed60ae 100644
--- a/riscv/insns/vlhuff_v.h
+++ b/riscv/insns/vlhuff_v.h
@@ -1,2 +1,2 @@
-// vlhuff.v and vlseg[2-8]huff.v
-VI_LDST_FF(uint, 16);
+// vlhuff.v
+VI_LDST_FF(uint, 16, false);
diff --git a/riscv/insns/vlsb_v.h b/riscv/insns/vlsb_v.h
index fd57bbe..1da0fc6 100644
--- a/riscv/insns/vlsb_v.h
+++ b/riscv/insns/vlsb_v.h
@@ -1,3 +1,3 @@
-// vlsb.v and vlsseg[2-8]b.v
+// vlsb.v
 require(P.VU.vsew >= e8);
-VI_LD(i * RS2, fn, int8, 1);
+VI_LD(i * RS2, fn, int8, 1, false);
diff --git a/riscv/insns/vlsbu_v.h b/riscv/insns/vlsbu_v.h
index 4376833..d92eb19 100644
--- a/riscv/insns/vlsbu_v.h
+++ b/riscv/insns/vlsbu_v.h
@@ -1,3 +1,3 @@
-// vlsb.v and vlsseg[2-8]b.v
+// vlsb.v
 require(P.VU.vsew >= e8);
-VI_LD(i * RS2, fn, uint8, 1);
+VI_LD(i * RS2, fn, uint8, 1, false);
diff --git a/riscv/insns/vlse_v.h b/riscv/insns/vlse_v.h
index 2ac2f29..ff33dc9 100644
--- a/riscv/insns/vlse_v.h
+++ b/riscv/insns/vlse_v.h
@@ -2,12 +2,12 @@
 reg_t sew = P.VU.vsew;
 
 if (sew == e8) {
-  VI_LD(i * RS2, fn, int8, 1);
+  VI_LD(i * RS2, fn, int8, 1, true);
 } else if (sew == e16) {
-  VI_LD(i * RS2, fn, int16, 2);
+  VI_LD(i * RS2, fn, int16, 2, true);
 } else if (sew == e32) {
-  VI_LD(i * RS2, fn, int32, 4);
+  VI_LD(i * RS2, fn, int32, 4, true);
 } else if (sew == e64) {
-  VI_LD(i * RS2, fn, int64, 8);
+  VI_LD(i * RS2, fn, int64, 8, true);
 }
 
diff --git a/riscv/insns/vlsh_v.h b/riscv/insns/vlsh_v.h
index 2834353..b9ab586 100644
--- a/riscv/insns/vlsh_v.h
+++ b/riscv/insns/vlsh_v.h
@@ -1,3 +1,3 @@
-// vlsh.v and vlsseg[2-8]h.v
+// vlsh.v
 require(P.VU.vsew >= e16);
-VI_LD(i * RS2, fn, int16, 2);
+VI_LD(i * RS2, fn, int16, 2, false);
diff --git a/riscv/insns/vlshu_v.h b/riscv/insns/vlshu_v.h
index 9b11b66..9e61e53 100644
--- a/riscv/insns/vlshu_v.h
+++ b/riscv/insns/vlshu_v.h
@@ -1,3 +1,3 @@
-// vlsh.v and vlsseg[2-8]h.v
+// vlsh.v
 require(P.VU.vsew >= e16);
-VI_LD(i * RS2, fn, uint16, 2);
+VI_LD(i * RS2, fn, uint16, 2, false);
diff --git a/riscv/insns/vlsw_v.h b/riscv/insns/vlsw_v.h
index 6681acb..14dba97 100644
--- a/riscv/insns/vlsw_v.h
+++ b/riscv/insns/vlsw_v.h
@@ -1,3 +1,3 @@
-// vlsw.v and vlsseg[2-8]w.v
+// vlsw.v
 require(P.VU.vsew >= e32);
-VI_LD(i * RS2, fn, int32, 4);
+VI_LD(i * RS2, fn, int32, 4, false);
diff --git a/riscv/insns/vlswu_v.h b/riscv/insns/vlswu_v.h
index 865af22..f509076 100644
--- a/riscv/insns/vlswu_v.h
+++ b/riscv/insns/vlswu_v.h
@@ -1,3 +1,3 @@
-// vlsw.v and vlsseg[2-8]w.v
+// vlsw.v
 require(P.VU.vsew >= e32);
-VI_LD(i * RS2, fn, uint32, 4);
+VI_LD(i * RS2, fn, uint32, 4, false);
diff --git a/riscv/insns/vlw_v.h b/riscv/insns/vlw_v.h
index b62f3d0..8970cd4 100644
--- a/riscv/insns/vlw_v.h
+++ b/riscv/insns/vlw_v.h
@@ -1,3 +1,3 @@
-// vlw.v and vlseg[2-8]w.v
+// vlw.v
 require(P.VU.vsew >= e32);
-VI_LD(0, i * nf + fn, int32, 4);
+VI_LD(0, i * nf + fn, int32, 4, false);
diff --git a/riscv/insns/vlwff_v.h b/riscv/insns/vlwff_v.h
index b671b01..ca224b6 100644
--- a/riscv/insns/vlwff_v.h
+++ b/riscv/insns/vlwff_v.h
@@ -1,3 +1,2 @@
 // vlwff.v
-// vlw.v and vlseg[2-8]wff.v
-VI_LDST_FF(int, 32);
+VI_LDST_FF(int, 32, false);
diff --git a/riscv/insns/vlwu_v.h b/riscv/insns/vlwu_v.h
index a4f8329..c1c77ff 100644
--- a/riscv/insns/vlwu_v.h
+++ b/riscv/insns/vlwu_v.h
@@ -1,3 +1,3 @@
-// vlwu.v and vlseg[2-8]wu.v
+// vlwu.v
 require(P.VU.vsew >= e32);
-VI_LD(0, i * nf + fn, uint32, 4);
+VI_LD(0, i * nf + fn, uint32, 4, false);
diff --git a/riscv/insns/vlwuff_v.h b/riscv/insns/vlwuff_v.h
index d50cb69..eb2cba3 100644
--- a/riscv/insns/vlwuff_v.h
+++ b/riscv/insns/vlwuff_v.h
@@ -1,2 +1,2 @@
-// vlwuff.v and vlseg[2-8]wuff.v
-VI_LDST_FF(uint, 32);
+// vlwuff.v
+VI_LDST_FF(uint, 32, false);
diff --git a/riscv/insns/vlxb_v.h b/riscv/insns/vlxb_v.h
index 768ecd3..449d918 100644
--- a/riscv/insns/vlxb_v.h
+++ b/riscv/insns/vlxb_v.h
@@ -1,4 +1,4 @@
-// vlxb.v and vlsseg[2-8]b.v
+// vlxb.v
 require(P.VU.vsew >= e8);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD_INDEX(index[i], fn, int8, 1);
+VI_LD_INDEX(index[i], fn, int8, 1, false);
diff --git a/riscv/insns/vlxbu_v.h b/riscv/insns/vlxbu_v.h
index 1bcd04c..72735d6 100644
--- a/riscv/insns/vlxbu_v.h
+++ b/riscv/insns/vlxbu_v.h
@@ -1,4 +1,4 @@
-// vlxbu.v and vlxseg[2-8]bu.v
+// vlxbu.v
 require(P.VU.vsew >= e8);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD_INDEX(index[i], fn, uint8, 1);
+VI_LD_INDEX(index[i], fn, uint8, 1, false);
diff --git a/riscv/insns/vlxe_v.h b/riscv/insns/vlxe_v.h
index 8035549..889a19e 100644
--- a/riscv/insns/vlxe_v.h
+++ b/riscv/insns/vlxe_v.h
@@ -2,11 +2,11 @@
 reg_t sew = P.VU.vsew;
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 if (sew == e8) {
-  VI_LD_INDEX(index[i], fn, int8, 1);
+  VI_LD_INDEX(index[i], fn, int8,  1, true);
 } else if (sew == e16) {
-  VI_LD_INDEX(index[i], fn, int16, 2);
+  VI_LD_INDEX(index[i], fn, int16, 2, true);
 } else if (sew == e32) {
-  VI_LD_INDEX(index[i], fn, int32, 4);
+  VI_LD_INDEX(index[i], fn, int32, 4, true);
 } else if (sew == e64) {
-  VI_LD_INDEX(index[i], fn, int64, 8);
+  VI_LD_INDEX(index[i], fn, int64, 8, true);
 }
diff --git a/riscv/insns/vlxh_v.h b/riscv/insns/vlxh_v.h
index e51b19f..fd3a1fb 100644
--- a/riscv/insns/vlxh_v.h
+++ b/riscv/insns/vlxh_v.h
@@ -1,4 +1,4 @@
-// vlxh.v and vlxseg[2-8]h.v
+// vlxh.v
 require(P.VU.vsew >= e16);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD_INDEX(index[i], fn, int16, 2);
+VI_LD_INDEX(index[i], fn, int16, 2, false);
diff --git a/riscv/insns/vlxhu_v.h b/riscv/insns/vlxhu_v.h
index 1ca6171..25cb7ab 100644
--- a/riscv/insns/vlxhu_v.h
+++ b/riscv/insns/vlxhu_v.h
@@ -1,4 +1,4 @@
-// vlxh.v and vlxseg[2-8]h.v
+// vlxhu.v
 require(P.VU.vsew >= e16);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD_INDEX(index[i], fn, uint16, 2);
+VI_LD_INDEX(index[i], fn, uint16, 2, false);
diff --git a/riscv/insns/vlxw_v.h b/riscv/insns/vlxw_v.h
index c2af748..8bc613b 100644
--- a/riscv/insns/vlxw_v.h
+++ b/riscv/insns/vlxw_v.h
@@ -1,4 +1,4 @@
-// vlxw.v and vlxseg[2-8]w.v
+// vlxw.v
 require(P.VU.vsew >= e32);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD_INDEX(index[i], fn, int32, 4);
+VI_LD_INDEX(index[i], fn, int32, 4, false);
diff --git a/riscv/insns/vlxwu_v.h b/riscv/insns/vlxwu_v.h
index fb8dc11..bccec95 100644
--- a/riscv/insns/vlxwu_v.h
+++ b/riscv/insns/vlxwu_v.h
@@ -1,4 +1,4 @@
-// vlxwu.v and vlxseg[2-8]wu.v
+// vlxwu.v
 require(P.VU.vsew >= e32);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD_INDEX(index[i], fn, uint32, 4);
+VI_LD_INDEX(index[i], fn, uint32, 4, false);