diff options
author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-13 01:21:20 -0700 |
---|---|---|
committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-14 19:25:45 -0700 |
commit | 544db5e040ae268faeb90b8a535077e4266b5774 (patch) | |
tree | 6bfd816f86dcbc9787ca626c14a4c0f5f32bb997 /riscv | |
parent | 439240bbeccb620d1ed4e63006b275e94a25fe4e (diff) | |
download | spike-544db5e040ae268faeb90b8a535077e4266b5774.zip spike-544db5e040ae268faeb90b8a535077e4266b5774.tar.gz spike-544db5e040ae268faeb90b8a535077e4266b5774.tar.bz2 |
rvv: add vfslide1[down|up].vf and refine checking rule
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 9 | ||||
-rw-r--r-- | riscv/encoding.h | 6 | ||||
-rw-r--r-- | riscv/insns/vfslide1down_vf.h | 28 | ||||
-rw-r--r-- | riscv/insns/vfslide1up_vf.h | 28 | ||||
-rw-r--r-- | riscv/insns/vslide1down_vx.h | 5 | ||||
-rw-r--r-- | riscv/insns/vslide1up_vx.h | 6 | ||||
-rw-r--r-- | riscv/insns/vslidedown_vi.h | 5 | ||||
-rw-r--r-- | riscv/insns/vslidedown_vx.h | 5 | ||||
-rw-r--r-- | riscv/insns/vslideup_vi.h | 6 | ||||
-rw-r--r-- | riscv/insns/vslideup_vx.h | 6 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 2 |
11 files changed, 79 insertions, 27 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index feaf2d4..1e03b59 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -506,6 +506,15 @@ static inline bool is_overlapped(const int astart, const int asize, require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ require(P.VU.vstart == 0); \ +#define VI_CHECK_SLIDE(is_over) \ + require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ + require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ + if (insn.v_vm() == 0 && P.VU.vlmul > 1) \ + require(insn.rd() != 0); \ + if (is_over) \ + require(insn.rd() != insn.rs2()); \ + + // // vector: loop header and end helper // diff --git a/riscv/encoding.h b/riscv/encoding.h index c052c6f..584bc27 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -932,6 +932,10 @@ #define MASK_VFSGNJN_VF 0xfc00707f #define MATCH_VFSGNJX_VF 0x28005057 #define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f #define MATCH_VFMV_S_F 0x42005057 #define MASK_VFMV_S_F 0xfff0707f #define MATCH_VFMERGE_VFM 0x5c005057 @@ -2209,6 +2213,8 @@ DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) diff --git a/riscv/insns/vfslide1down_vf.h b/riscv/insns/vfslide1down_vf.h new file mode 100644 index 0000000..b6c1735 --- /dev/null +++ b/riscv/insns/vfslide1down_vf.h @@ -0,0 +1,28 @@ +//vfslide1down.vf vd, vs2, rs1 +VI_CHECK_SLIDE(false); + +VI_VFP_LOOP_BASE +if (i != vl - 1) { + switch (P.VU.vsew) { + case e32: { + VI_XI_SLIDEDOWN_PARAMS(e32, 1); + vd = vs2; + } + break; + case e64: { + VI_XI_SLIDEDOWN_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (P.VU.vsew) { + case e32: + P.VU.elt<float32_t>(rd_num, vl - 1) = f32(FRS1); + break; + case e64: + P.VU.elt<float64_t>(rd_num, vl - 1) = f64(FRS1); + break; + } +} +VI_VFP_LOOP_END diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h new file mode 100644 index 0000000..40b26e1 --- /dev/null +++ b/riscv/insns/vfslide1up_vf.h @@ -0,0 +1,28 @@ +//vfslide1up.vf vd, vs2, rs1 +VI_CHECK_SLIDE(true); + +VI_VFP_LOOP_BASE +if (i != 0) { + switch (P.VU.vsew) { + case e32: { + VI_XI_SLIDEUP_PARAMS(e32, 1); + vd = vs2; + } + break; + case e64: { + VI_XI_SLIDEUP_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (P.VU.vsew) { + case e32: + P.VU.elt<float32_t>(rd_num, 0) = f32(FRS1); + break; + case e64: + P.VU.elt<float64_t>(rd_num, 0) = f64(FRS1); + break; + } +} +VI_VFP_LOOP_END diff --git a/riscv/insns/vslide1down_vx.h b/riscv/insns/vslide1down_vx.h index 04e2540..1fe9d04 100644 --- a/riscv/insns/vslide1down_vx.h +++ b/riscv/insns/vslide1down_vx.h @@ -1,8 +1,5 @@ //vslide1down.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -if (P.VU.vlmul > 1 && insn.v_vm() == 0) - require(insn.rd() != 0); +VI_CHECK_SLIDE(false); VI_LOOP_BASE if (i != vl - 1) { diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 5154259..6f12528 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -1,9 +1,5 @@ //vslide1up.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0 && P.VU.vlmul > 1) - require(insn.rd() != 0); +VI_CHECK_SLIDE(true); VI_LOOP_BASE if (i != 0) { diff --git a/riscv/insns/vslidedown_vi.h b/riscv/insns/vslidedown_vi.h index dd58c1e..bc440cf 100644 --- a/riscv/insns/vslidedown_vi.h +++ b/riscv/insns/vslidedown_vi.h @@ -1,8 +1,5 @@ // vslidedown.vi vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -if (P.VU.vlmul > 1 && insn.v_vm() == 0) - require(insn.rd() != 0); +VI_CHECK_SLIDE(false); const reg_t sh = insn.v_zimm5(); VI_LOOP_BASE diff --git a/riscv/insns/vslidedown_vx.h b/riscv/insns/vslidedown_vx.h index 744a7a5..074aa50 100644 --- a/riscv/insns/vslidedown_vx.h +++ b/riscv/insns/vslidedown_vx.h @@ -1,8 +1,5 @@ //vslidedown.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -if (P.VU.vlmul > 1 && insn.v_vm() == 0) - require(insn.rd() != 0); +VI_CHECK_SLIDE(false); const uint128_t sh = RS1; VI_LOOP_BASE diff --git a/riscv/insns/vslideup_vi.h b/riscv/insns/vslideup_vi.h index 99d30bc..4265789 100644 --- a/riscv/insns/vslideup_vi.h +++ b/riscv/insns/vslideup_vi.h @@ -1,9 +1,5 @@ // vslideup.vi vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0 && P.VU.vlmul > 1) - require(insn.rd() != 0); +VI_CHECK_SLIDE(true); const reg_t offset = insn.v_zimm5(); VI_LOOP_BASE diff --git a/riscv/insns/vslideup_vx.h b/riscv/insns/vslideup_vx.h index 2d68a39..720d2ab 100644 --- a/riscv/insns/vslideup_vx.h +++ b/riscv/insns/vslideup_vx.h @@ -1,9 +1,5 @@ //vslideup.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0 && P.VU.vlmul > 1) - require(insn.rd() != 0); +VI_CHECK_SLIDE(true); const reg_t offset = RS1; VI_LOOP_BASE diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 757c734..bbcba5e 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -565,6 +565,8 @@ riscv_insn_ext_v_alu_fp = \ vfsgnjx_vf \ vfsgnjx_vv \ vfsqrt_v \ + vfslide1down_vf \ + vfslide1up_vf \ vfsub_vf \ vfsub_vv \ vfwadd_vf \ |