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authorChih-Min Chao <chihmin.chao@sifive.com>2020-04-06 22:30:12 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-04-15 10:04:37 -0700
commit0735b28f548e670f1bdb9c3ec6f3becc5da3c77d (patch)
tree4eee19e3488286ae524bae3ad1b953c9d489a7ac /riscv
parent770b20672e98b8a12ce72a4a682a9cbf05616e06 (diff)
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rvv: add narrow conversion instrucitons
know issue: There is no f32_to_u[i]16 conversion function in softfloat. The implementation use f32_to_u[i]16 to work around and will be fixed after the related APIs are available miss f32_to_[u]i16 function Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r--riscv/decode.h27
-rw-r--r--riscv/insns/vfncvt_f_f_w.h15
-rw-r--r--riscv/insns/vfncvt_f_x_w.h14
-rw-r--r--riscv/insns/vfncvt_f_xu_w.h14
-rw-r--r--riscv/insns/vfncvt_rod_f_f_w.h15
-rw-r--r--riscv/insns/vfncvt_x_f_w.h14
-rw-r--r--riscv/insns/vfncvt_xu_f_w.h14
7 files changed, 71 insertions, 42 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index 424d0f7..87d7748 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2009,6 +2009,33 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
DEBUG_RVV_FP_VV; \
VI_VFP_LOOP_END
+#define VI_VFP_CVT_SCALE(BODY16, BODY32, is_widen) \
+ if (is_widen) { \
+ VI_CHECK_DSS(false);\
+ } else { \
+ VI_CHECK_SDS(false); \
+ } \
+ require((P.VU.vsew == e16 && p->supports_extension('F')) || \
+ (P.VU.vsew == e32 && p->supports_extension('D'))); \
+ switch(P.VU.vsew) { \
+ case e16: {\
+ VI_VFP_LOOP_BASE \
+ BODY16 \
+ set_fp_exceptions; \
+ VI_VFP_LOOP_END \
+ } \
+ break; \
+ case e32: {\
+ VI_VFP_LOOP_BASE \
+ BODY32 \
+ set_fp_exceptions; \
+ VI_VFP_LOOP_END \
+ } \
+ break; \
+ default: \
+ require(0); \
+ break; \
+ }
#define DEBUG_START 0x0
#define DEBUG_END (0x1000 - 1)
diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h
index 3a9ead3..d5d5de6 100644
--- a/riscv/insns/vfncvt_f_f_w.h
+++ b/riscv/insns/vfncvt_f_f_w.h
@@ -1,10 +1,11 @@
// vfncvt.f.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
- require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+ auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+ P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
+},
+{
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
- set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
+
diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h
index c328395..25faa1e 100644
--- a/riscv/insns/vfncvt_f_x_w.h
+++ b/riscv/insns/vfncvt_f_x_w.h
@@ -1,10 +1,10 @@
// vfncvt.f.x.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
- require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+ auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
+ P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
+},
+{
auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i, true) = i64_to_f32(vs2);
- set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h
index c674644..a8b62fe 100644
--- a/riscv/insns/vfncvt_f_xu_w.h
+++ b/riscv/insns/vfncvt_f_xu_w.h
@@ -1,10 +1,10 @@
// vfncvt.f.xu.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
- require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+ auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
+ P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
+},
+{
auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i, true) = ui64_to_f32(vs2);
- set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h
index 0eae343..77501e6 100644
--- a/riscv/insns/vfncvt_rod_f_f_w.h
+++ b/riscv/insns/vfncvt_rod_f_f_w.h
@@ -1,11 +1,12 @@
// vfncvt.f.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
- require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+ softfloat_roundingMode = softfloat_round_odd;
+ auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+ P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
+},
+{
softfloat_roundingMode = softfloat_round_odd;
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
- set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h
index d6728bd..b7a7e42 100644
--- a/riscv/insns/vfncvt_x_f_w.h
+++ b/riscv/insns/vfncvt_x_f_w.h
@@ -1,10 +1,10 @@
// vfncvt.x.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
- require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+ auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+ P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i32(vs2, STATE.frm, true);
+},
+{
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true);
- set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h
index f2cce24..0673b35 100644
--- a/riscv/insns/vfncvt_xu_f_w.h
+++ b/riscv/insns/vfncvt_xu_f_w.h
@@ -1,10 +1,10 @@
// vfncvt.xu.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
- require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+ auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+ P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui32(vs2, STATE.frm, true);
+},
+{
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true);
- set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)