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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-20 01:07:32 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-20 01:07:41 -0700 |
| commit | c1720d51ca2caa90dba4f37a0528b748c2212742 (patch) | |
| tree | f8af327663678cbcddbb2e724eae8abbe622312e /riscv | |
| parent | a09a86cf1386cbe57895d1a25de11b8431134dbb (diff) | |
| download | spike-c1720d51ca2caa90dba4f37a0528b748c2212742.zip spike-c1720d51ca2caa90dba4f37a0528b748c2212742.tar.gz spike-c1720d51ca2caa90dba4f37a0528b748c2212742.tar.bz2 | |
rvv: refine vfncvt case for f32_to_[u]i16 cases
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/vfncvt_rtz_x_f_w.h | 3 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_rtz_xu_f_w.h | 3 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_x_f_w.h | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h index 7fc841c..70c66d1 100644 --- a/riscv/insns/vfncvt_rtz_x_f_w.h +++ b/riscv/insns/vfncvt_rtz_x_f_w.h @@ -1,9 +1,8 @@ // vfncvt.rtz.x.f.w vd, vs2, vm VI_VFP_CVT_SCALE ({ - require(0); auto vs2 = P.VU.elt<float32_t>(rs2_num, i); - //P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true); + P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true); }, { auto vs2 = P.VU.elt<float64_t>(rs2_num, i); diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h index 470dab2..98f1c4b 100644 --- a/riscv/insns/vfncvt_rtz_xu_f_w.h +++ b/riscv/insns/vfncvt_rtz_xu_f_w.h @@ -1,9 +1,8 @@ // vfncvt.rtz.xu.f.w vd, vs2, vm VI_VFP_CVT_SCALE ({ - require(0); auto vs2 = P.VU.elt<float32_t>(rs2_num, i); - //P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, softfloat_round_minMag, true); + P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, softfloat_round_minMag, true); }, { auto vs2 = P.VU.elt<float64_t>(rs2_num, i); diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h index 714b76a..3ddbb87 100644 --- a/riscv/insns/vfncvt_x_f_w.h +++ b/riscv/insns/vfncvt_x_f_w.h @@ -1,9 +1,8 @@ // vfncvt.x.f.w vd, vs2, vm VI_VFP_CVT_SCALE ({ - require(0); auto vs2 = P.VU.elt<float32_t>(rs2_num, i); - //P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, STATE.frm, true); + P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, STATE.frm, true); }, { auto vs2 = P.VU.elt<float64_t>(rs2_num, i); |