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2020-05-20rvv: refine st_indexChih-Min Chao8-184/+8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: refine ld_indexChih-Min Chao4-91/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: vid's mlen overlap checkingDave.Wen1-1/+1
2020-05-14rvv: add vzext/vsextChih-Min Chao6-0/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: amo: fix wrong index eewChih-Min Chao27-27/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: change to 0.9amoChih-Min Chao45-18/+72
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: amo pre-0.9Chih-Min Chao9-0/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-11rvv: change to 0.9 ldstChih-Min Chao75-204/+328
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen1-1/+5
2020-05-04zfh: implementation all instructionsChih-Min Chao36-0/+167
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27rvv: commitlog: fix comparision dst informationChih-Min Chao2-2/+2
Comparison only writes one vector register Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-24rvv: commitlog: fix missing informaiton for slide1Chih-Min Chao4-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-23rvv: fix vfncvt.xu.f.w for fp16Chih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-23rvv: aad fp16 support for vfwxxx.[wv]vChih-Min Chao9-0/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-22rvv: fix segment load/store nf checkingChih-Min Chao1-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix vfmv for fp16Chih-Min Chao3-13/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix vfmerge.vfm for fp16Chih-Min Chao1-2/+15
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix vfslide for fp16Chih-Min Chao2-0/+16
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-21rvv: fix floating comparison for fp16Chih-Min Chao9-0/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-20rvv: refine vfncvt case for f32_to_[u]i16 casesChih-Min Chao3-6/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-20rvv: fix f16_to_[u]i16 conversionChih-Min Chao4-8/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-20rvv: remove debug messageChih-Min Chao1-1/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-19rvv: fix vfwredsum checking ruleChih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-16rvv: fix rtz cvtChih-Min Chao13-51/+47
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15rvv: add widen conversion instructionsChih-Min Chao7-51/+53
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15rvv: add narrow conversion instrucitonsChih-Min Chao6-42/+44
know issue: There is no f32_to_u[i]16 conversion function in softfloat. The implementation use f32_to_u[i]16 to work around and will be fixed after the related APIs are available miss f32_to_[u]i16 function Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15rvv: add normal and widen reduction instructionsChih-Min Chao6-12/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15rvv: add vmfxx f16 compare instructionsChih-Min Chao10-0/+30
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15rvv: add .vf fp16 instructionsChih-Min Chao24-0/+76
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15rvv: add .vv fp16 instructionsChih-Min Chao21-0/+63
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: leave only SEW-bit segment storeChih-Min Chao16-151/+51
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: leave only sew-wise segment loadChih-Min Chao28-65/+64
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao8-27/+62
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao6-0/+64
new features in spec 0.9 ref: https://github.com/riscv/riscv-v-spec/issues/352 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-10rvv: vslide[1]up now allows mask overlap when LMUL=1Chih-Min Chao3-3/+3
See https://github.com/riscv/riscv-v-spec/pull/407 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-05Don't acquire load reservation in the event of a faultAndrew Waterman2-2/+4
I think this bug wasn't caught because OS code never steps over faulting LR instructions in practice. The exception is either fatal (in which case the point is moot) or the LR is re-executed (in which case the point is also moot). Resolves #431
2020-04-05ebreak should write mtval with 0, not pcAndrew Waterman2-2/+2
Resolves #426 The relevant passage in the spec does not mention software breakpoints as one of the cases that cause mtval to be set to a nonzero value: https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202
2020-03-27rvv: fix int_max/min value calculationChih-Min Chao8-23/+26
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-26rvv: fix vssraa.vi e64 corner caseChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-24rvv: fix vmv reg checking failureChih-Min Chao3-1/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23rvv: restrict segment load register ruleChih-Min Chao3-0/+3
For unit-strided and stride segment load, mask register can't overlap destination register if masked Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-17rvv: fix vdiv corner caseChih-Min Chao2-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-12rvv: commitlog: fix vrgather_vv dumpChih-Min Chao1-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-12rvv: fix vfmv.f.s and vfmv.s.fChih-Min Chao2-22/+21
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao7-25/+28
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-11rvv: respect vstart and vl for vfmv.s.fChih-Min Chao1-19/+22
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei2-13/+24
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei4-14/+47
The number of vector FP ALUs and implementations of vf(w)redsum could be passed as options by the following example: "--varch=vlen:512,elen:32,slen:512,nalu:4,fredsum-impl:parallel" By default, 4 of vector FP ALUs and ordered vector FP reduction sum implementations are assumed.
2020-03-03rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
The spec doesn't limit the range of middle value. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei6-16/+16
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