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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-23 21:10:37 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-23 21:21:40 -0700 |
commit | 693532f976e073d13e082dd0c30ab6d2c66cf11b (patch) | |
tree | ff37c53133d7389e6b42b6eb23def81c3dfdf3dc /riscv/insns | |
parent | 6124093ce812364aa40243bdac6004883993cc39 (diff) | |
download | spike-693532f976e073d13e082dd0c30ab6d2c66cf11b.zip spike-693532f976e073d13e082dd0c30ab6d2c66cf11b.tar.gz spike-693532f976e073d13e082dd0c30ab6d2c66cf11b.tar.bz2 |
rvv: aad fp16 support for vfwxxx.[wv]v
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns')
-rw-r--r-- | riscv/insns/vfwadd_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwadd_wv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwmacc_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwmsac_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwmul_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwnmacc_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwnmsac_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwsub_vv.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfwsub_wv.h | 3 |
9 files changed, 27 insertions, 0 deletions
diff --git a/riscv/insns/vfwadd_vv.h b/riscv/insns/vfwadd_vv.h index 0665cdc..7255a50 100644 --- a/riscv/insns/vfwadd_vv.h +++ b/riscv/insns/vfwadd_vv.h @@ -1,5 +1,8 @@ // vfwadd.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_add(vs2, vs1); +}, +{ vd = f64_add(vs2, vs1); }) diff --git a/riscv/insns/vfwadd_wv.h b/riscv/insns/vfwadd_wv.h index 675ef22..c1ed038 100644 --- a/riscv/insns/vfwadd_wv.h +++ b/riscv/insns/vfwadd_wv.h @@ -1,5 +1,8 @@ // vfwadd.wv vd, vs2, vs1 VI_VFP_WV_LOOP_WIDE ({ + vd = f32_add(vs2, vs1); +}, +{ vd = f64_add(vs2, vs1); }) diff --git a/riscv/insns/vfwmacc_vv.h b/riscv/insns/vfwmacc_vv.h index 99839af..a654198 100644 --- a/riscv/insns/vfwmacc_vv.h +++ b/riscv/insns/vfwmacc_vv.h @@ -1,5 +1,8 @@ // vfwmacc.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_mulAdd(vs1, vs2, vd); +}, +{ vd = f64_mulAdd(vs1, vs2, vd); }) diff --git a/riscv/insns/vfwmsac_vv.h b/riscv/insns/vfwmsac_vv.h index 8157170..9dc4073 100644 --- a/riscv/insns/vfwmsac_vv.h +++ b/riscv/insns/vfwmsac_vv.h @@ -1,5 +1,8 @@ // vfwmsac.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN)); +}, +{ vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN)); }) diff --git a/riscv/insns/vfwmul_vv.h b/riscv/insns/vfwmul_vv.h index f8e717e..2ce38e6 100644 --- a/riscv/insns/vfwmul_vv.h +++ b/riscv/insns/vfwmul_vv.h @@ -1,5 +1,8 @@ // vfwmul.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_mul(vs2, vs1); +}, +{ vd = f64_mul(vs2, vs1); }) diff --git a/riscv/insns/vfwnmacc_vv.h b/riscv/insns/vfwnmacc_vv.h index 3dcba1d..bf863e0 100644 --- a/riscv/insns/vfwnmacc_vv.h +++ b/riscv/insns/vfwnmacc_vv.h @@ -1,5 +1,8 @@ // vfwnmacc.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN)); +}, +{ vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); }) diff --git a/riscv/insns/vfwnmsac_vv.h b/riscv/insns/vfwnmsac_vv.h index d2447e1..ce97749 100644 --- a/riscv/insns/vfwnmsac_vv.h +++ b/riscv/insns/vfwnmsac_vv.h @@ -1,5 +1,8 @@ // vfwnmsac.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd); +}, +{ vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd); }) diff --git a/riscv/insns/vfwsub_vv.h b/riscv/insns/vfwsub_vv.h index 0a72fea..ce08e36 100644 --- a/riscv/insns/vfwsub_vv.h +++ b/riscv/insns/vfwsub_vv.h @@ -1,5 +1,8 @@ // vfwsub.vv vd, vs2, vs1 VI_VFP_VV_LOOP_WIDE ({ + vd = f32_sub(vs2, vs1); +}, +{ vd = f64_sub(vs2, vs1); }) diff --git a/riscv/insns/vfwsub_wv.h b/riscv/insns/vfwsub_wv.h index 4c6fcf6..eef904d 100644 --- a/riscv/insns/vfwsub_wv.h +++ b/riscv/insns/vfwsub_wv.h @@ -1,5 +1,8 @@ // vfwsub.wv vd, vs2, vs1 VI_VFP_WV_LOOP_WIDE ({ + vd = f32_sub(vs2, vs1); +}, +{ vd = f64_sub(vs2, vs1); }) |