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| author | Dave.Wen <dave.wen@sifive.com> | 2020-05-07 05:59:07 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2020-05-07 05:59:07 -0700 |
| commit | 3baafbe3559fb62b8a4d3f13288593035e4502d3 (patch) | |
| tree | 42f99317b2b11c2fe1e3a8f79de8a1852e4d4cdb /riscv/insns | |
| parent | f471e0edac1be60e92b96518cb653fa5f173af07 (diff) | |
| download | spike-3baafbe3559fb62b8a4d3f13288593035e4502d3.zip spike-3baafbe3559fb62b8a4d3f13288593035e4502d3.tar.gz spike-3baafbe3559fb62b8a4d3f13288593035e4502d3.tar.bz2 | |
rvv: add eew and lmul for vle/vse/vleff
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/vse_v.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/insns/vse_v.h b/riscv/insns/vse_v.h index bcb1b21..cdb07bd 100644 --- a/riscv/insns/vse_v.h +++ b/riscv/insns/vse_v.h @@ -1,7 +1,11 @@ // vse.v and vsseg[2-8]e.v reg_t sew = P.VU.vsew; -if (sew == e8) { +const reg_t mew = insn.v_mew(); +const reg_t width = insn.v_width(); +VI_EEW(mew, width); + +if (P.VU.veew == e8) { VI_ST(0, (i * nf + fn), uint8, 1, true); } else if (sew == e16) { VI_ST(0, (i * nf + fn), uint16, 2, true); |