rvv: add narrow conversion instrucitons

know issue:
   There is no f32_to_u[i]16 conversion function in softfloat. The
   implementation use f32_to_u[i]16 to work around and will be fixed
   after the related APIs are available

miss f32_to_[u]i16 function
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

6 files changed, 44 insertions, 42 deletions

diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h
index 3a9ead3..d5d5de6 100644
--- a/riscv/insns/vfncvt_f_f_w.h
+++ b/riscv/insns/vfncvt_f_f_w.h
@@ -1,10 +1,11 @@
 // vfncvt.f.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
+
diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h
index c328395..25faa1e 100644
--- a/riscv/insns/vfncvt_f_x_w.h
+++ b/riscv/insns/vfncvt_f_x_w.h
@@ -1,10 +1,10 @@
 // vfncvt.f.x.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = i64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h
index c674644..a8b62fe 100644
--- a/riscv/insns/vfncvt_f_xu_w.h
+++ b/riscv/insns/vfncvt_f_xu_w.h
@@ -1,10 +1,10 @@
 // vfncvt.f.xu.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = ui64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h
index 0eae343..77501e6 100644
--- a/riscv/insns/vfncvt_rod_f_f_w.h
+++ b/riscv/insns/vfncvt_rod_f_f_w.h
@@ -1,11 +1,12 @@
 // vfncvt.f.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  softfloat_roundingMode = softfloat_round_odd;
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
+},
+{
   softfloat_roundingMode = softfloat_round_odd;
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h
index d6728bd..b7a7e42 100644
--- a/riscv/insns/vfncvt_x_f_w.h
+++ b/riscv/insns/vfncvt_x_f_w.h
@@ -1,10 +1,10 @@
 // vfncvt.x.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i32(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h
index f2cce24..0673b35 100644
--- a/riscv/insns/vfncvt_xu_f_w.h
+++ b/riscv/insns/vfncvt_xu_f_w.h
@@ -1,10 +1,10 @@
 // vfncvt.xu.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui32(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)