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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-19 23:57:58 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-20 00:03:02 -0700 |
| commit | 1a5c4868f7058f7e04c7f2e80a87ade65115e117 (patch) | |
| tree | 004919f19133c14e1fb6b4e51f0a2e6894883f72 /riscv/insns | |
| parent | adb4453324ef14ca1be3ecf1eae8492d1ff6ab8b (diff) | |
| download | spike-1a5c4868f7058f7e04c7f2e80a87ade65115e117.zip spike-1a5c4868f7058f7e04c7f2e80a87ade65115e117.tar.gz spike-1a5c4868f7058f7e04c7f2e80a87ade65115e117.tar.bz2 | |
rvv: fix f16_to_[u]i16 conversion
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/vfcvt_rtz_x_f_v.h | 3 | ||||
| -rw-r--r-- | riscv/insns/vfcvt_rtz_xu_f_v.h | 3 | ||||
| -rw-r--r-- | riscv/insns/vfcvt_x_f_v.h | 3 | ||||
| -rw-r--r-- | riscv/insns/vfcvt_xu_f_v.h | 3 |
4 files changed, 4 insertions, 8 deletions
diff --git a/riscv/insns/vfcvt_rtz_x_f_v.h b/riscv/insns/vfcvt_rtz_x_f_v.h index 46d2f90..e7241bd 100644 --- a/riscv/insns/vfcvt_rtz_x_f_v.h +++ b/riscv/insns/vfcvt_rtz_x_f_v.h @@ -1,8 +1,7 @@ // vfcvt.rtz.x.f.v vd, vd2, vm VI_VFP_VF_LOOP ({ - require(0); - //P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true); + P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true); }, { P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true); diff --git a/riscv/insns/vfcvt_rtz_xu_f_v.h b/riscv/insns/vfcvt_rtz_xu_f_v.h index 368d5e1..d3d266d 100644 --- a/riscv/insns/vfcvt_rtz_xu_f_v.h +++ b/riscv/insns/vfcvt_rtz_xu_f_v.h @@ -1,8 +1,7 @@ // vfcvt.rtz.xu.f.v vd, vd2, vm VI_VFP_VF_LOOP ({ - require(0); - //P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true); + P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true); }, { P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true); diff --git a/riscv/insns/vfcvt_x_f_v.h b/riscv/insns/vfcvt_x_f_v.h index 153afbc..01e5ca1 100644 --- a/riscv/insns/vfcvt_x_f_v.h +++ b/riscv/insns/vfcvt_x_f_v.h @@ -1,8 +1,7 @@ // vfcvt.x.f.v vd, vd2, vm VI_VFP_VF_LOOP ({ - require(0); - //P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm, true); + P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm, true); }, { P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); diff --git a/riscv/insns/vfcvt_xu_f_v.h b/riscv/insns/vfcvt_xu_f_v.h index 3f9a31b..725cbda 100644 --- a/riscv/insns/vfcvt_xu_f_v.h +++ b/riscv/insns/vfcvt_xu_f_v.h @@ -1,8 +1,7 @@ // vfcvt.xu.f.v vd, vd2, vm VI_VFP_VV_LOOP ({ - require(0); - //P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm, true); + P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm, true); }, { P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); |