rvv: add widen conversion instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

7 files changed, 53 insertions, 51 deletions

diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h
index 424f0f4..abb68a4 100644
--- a/riscv/insns/vfwcvt_f_f_v.h
+++ b/riscv/insns/vfwcvt_f_f_v.h
@@ -1,10 +1,10 @@
 // vfwcvt.f.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<float32_t>(rd_num, i, true) = f16_to_f32(vs2);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = f32_to_f64(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)
diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h
index 1c05ab7..62cd8e8 100644
--- a/riscv/insns/vfwcvt_f_x_v.h
+++ b/riscv/insns/vfwcvt_f_x_v.h
@@ -1,10 +1,10 @@
 // vfwcvt.f.x.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<int16_t>(rs2_num, i);
+  P.VU.elt<float32_t>(rd_num, i, true) = i32_to_f32(vs2);
+},
+{
   auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)
diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h
index fcb8c0c..36a81ed 100644
--- a/riscv/insns/vfwcvt_f_xu_v.h
+++ b/riscv/insns/vfwcvt_f_xu_v.h
@@ -1,10 +1,10 @@
 // vfwcvt.f.xu.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<uint16_t>(rs2_num, i);
+  P.VU.elt<float32_t>(rd_num, i, true) = ui32_to_f32(vs2);
+},
+{
   auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)
diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h
index 0afab8d..4c421c8 100644
--- a/riscv/insns/vfwcvt_rtz_x_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_x_f_v.h
@@ -1,11 +1,12 @@
-// vfwcvt.x.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfwcvt.rtz.x.f.v vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  softfloat_roundingMode = softfloat_round_minMag;
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, STATE.frm, true);
+},
+{
   softfloat_roundingMode = softfloat_round_minMag;
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)
diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h
index d6bbc48..894582d 100644
--- a/riscv/insns/vfwcvt_rtz_xu_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h
@@ -1,11 +1,12 @@
-// vfwcvt.xu.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfwcvt.rtz,xu.f.v vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  softfloat_roundingMode = softfloat_round_minMag;
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, STATE.frm, true);
+},
+{
   softfloat_roundingMode = softfloat_round_minMag;
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)
diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h
index 3df8256..9b79893 100644
--- a/riscv/insns/vfwcvt_x_f_v.h
+++ b/riscv/insns/vfwcvt_x_f_v.h
@@ -1,10 +1,10 @@
 // vfwcvt.x.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)
diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h
index 6e39b7d..bfe16ff 100644
--- a/riscv/insns/vfwcvt_xu_f_v.h
+++ b/riscv/insns/vfwcvt_xu_f_v.h
@@ -1,10 +1,10 @@
 // vfwcvt.xu.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_WIDE_END
+}, true)