aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv/Kconfig
AgeCommit message (Collapse)AuthorFilesLines
12 hoursriscv: cache: Add CBO instructionsMayuresh Chitale1-0/+4
Define CBO inval and flush instructions and use those for the dcache inval and flush operations respectively. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
15 hoursriscv: qemu: Explicitly advertise RVVM supportLekKit1-1/+1
This patch series enables full RVVM virtual machine support which was earlier inconveniently provided as out-of-tree patchset. This should be cleaner than a separate board config, since both emulators provide similar feature set. Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-16Merge tag 'v2024.10-rc5' into nextTom Rini1-0/+14
Prepare v2024.10-rc5
2024-09-11riscv: Add AST2700 SoC initial platform supportChia-Wei Wang1-0/+5
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11riscv: Make stack size shift configurableChia-Wei Wang1-1/+1
Add prompt for STACK_SIZE_SHIFT to make it configurable. The default value remains 14 as usual. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11riscv: Make A ISA extension selectableChia-Wei Wang1-1/+4
Make the Atomic (A) ISA extension selectable. Thus CPUs such as Ibex without the A extension can be supported. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-10riscv: show registers in crash dumps by defaultHeinrich Schuchardt1-0/+1
If an exception occurs in main U-Boot, show the registers. This makes analyzing crashes especially in external applications easier. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-10riscv: allow to enable SHOW_REGS in main U-Boot onlyHeinrich Schuchardt1-0/+12
To minimize SPL size it is reasonable to disable SHOW_REGS. For main U-Boot the size restrictions are much more relaxed. * Provide separate Kconfig symbols for SPL and main U-Boot. * Add a help text. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-10riscv: CONFIG_SPL_FRAMEPOINTER must depend on CONFIG_SPLHeinrich Schuchardt1-0/+1
The CONFIG_SPL_FRAMEPOINTER symbol is only relevant in SPL. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk>
2024-05-14andes: Unify naming policy for Andes related sourceLeo Yu-Chi Liang1-2/+2
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09riscv: Move virtio scan to board_late_init()Łukasz Stelmach1-0/+1
When virtio_init() gets called from board_init() PCI isn't ready. Thus, virtio-over-PCI (e.g. network interfaces) devices can't be detected and used without additional `virtio scan` scan in the shell or a script. Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09riscv: cpu: cv1800b: Add support for cv1800b SoCKongyang Liu1-0/+1
Add Sophgo cv1800b SoC to support RISC-V arch. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09riscv: add backtrace supportBen Dooks1-0/+20
When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Tested-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-13Kconfig: move CONFIG_32/64BIT to arch/KconfigDan Carpenter1-6/+0
These configs are used in multiple places so put them in a shared Kconfig file. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-31riscv: sophgo: milkv_duo: initial support addedKongyang Liu1-0/+4
Add support for Sophgo's Milk-V Duo board, only minimal device tree and serial console are enabled, and it can boot via vendor first stage bootloader. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-18riscv: Add support for AMD/Xilinx MicroBlaze VMichal Simek1-0/+4
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2023-11-02riscv: Sort target configs alphabeticallySamuel Holland1-9/+9
Clean things up for the next time somebody adds a target. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek1-1/+0
Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all default n/no options") and again sync is required. default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin1-0/+91
This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbolRandolph1-0/+8
Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-04configs: andes: add vender prefix for target nameRandolph1-2/+2
Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-10-04riscv: enable CONFIG_DEBUG_UART by defaultHeinrich Schuchardt1-0/+1
Most boards don't enable the pre-console buffer. So we will not see any early messages. OpenSBI 1.3 provides us with the debug console extension that can fill this gap. For S-Mode U-Boot enable CONFIG_DEBUG_UART by default. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-26riscv: set fdtfile on VisionFive 2Heinrich Schuchardt1-0/+1
Multiple revisions of the StarFive VisionFive 2 board exist. They can be identified by reading their EEPROM. Linux uses two differently named device-tree files. To load the correct device-tree we need to set $fdtfile to the device-tree file name that matches the board revision. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-08-10riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USEShengyu Qu1-0/+8
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-12riscv: t-head: licheepi4a: initial support addedYixun Lan1-0/+5
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial console are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot. Reviewed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng1-4/+4
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-12riscv: clint: Update the sifive clint ipi driver to support aclintBin Meng1-0/+4
This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang1-0/+5
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang1-4/+4
The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-15riscv: clarify meaning of CONFIG_SBI_V02Heinrich Schuchardt1-7/+7
Describe that CONFIG_SBI_V02=y does not mean SBI specification v0.2 but v0.2 or later. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin1-3/+3
As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20riscv: support building double-float modulesHeinrich Schuchardt1-0/+15
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen1-0/+7
In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-26spl: introduce SPL_XIP to configNikita Shubin1-0/+7
U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-04-06riscv: alloc space exhaustedHeinrich Schuchardt1-3/+0
When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message alloc space exhausted 32 is the current maximum number of harts for machine virt in QEMU 7.0. Raise the default for SYS_MALLOC_F_LEN to 16 KiB. Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini1-0/+5
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-07riscv: lib: implement enable_caches for sifive cacheZong Li1-0/+5
The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek1-2/+0
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31Finish converting CONFIG_SYS_CACHELINE_SIZE to KconfigTom Rini1-0/+2
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei1-0/+4
This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-31board: sifive: add HiFive Unmatched board supportGreen Wan1-0/+4
Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan1-0/+1
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-17riscv: Group assembly optimized implementation of memory routines into a submenuBin Meng1-0/+4
Currently all assembly optimized implementation of memory routines show up at the top level of the RISC-V architecture Kconfig menu. Let's group them together into a submenu. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng1-1/+8
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-08riscv: assembler versions of memcpy, memmove, memsetHeinrich Schuchardt1-0/+78
Provide optimized versions of memcpy(), memmove(), memset() copied from the Linux kernel. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-04-08riscv: sifive: Rename fu540 board to unleashedBin Meng1-3/+3
In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-01-18riscv: Add DMA 64-bit address supportPadmarao Begari1-0/+4
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: Move Andes PLMT driver to drivers/timerSean Anderson1-7/+0
This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: Only enable OF_BOARD_FIXUP for S-ModeSean Anderson1-1/+1
It is unsafe to enable OF_BOARD_FIXUP only based on OF_SEPARATE. OF_SEPARATE may indicate that the user wishes U-Boot to use a different device tree than one obtained via OF_PRIOR_STAGE. However, OF_SEPARATE may also indicate that the device tree which would be obtained via OF_PRIOR_STAGE is invalid, nonexistant, or otherwise unusable. In this latter case, enabling OF_BOARD_FIXUP will result in corruption of the device tree. To remedy this, only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode. Fixes: 1c17e55594a394ced7de88d91be294eaf8c564c1 Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-09-30riscv: Rework Sifive CLINT as UCLASS_TIMER driverSean Anderson1-4/+0
This converts the clint driver from the riscv-specific interface to be a DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously implicitly depended on the CLINT to select REGMAP. Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb), the SiFive CLINT is part of the device tree passed in by qemu. This device tree doesn't have a clocks or clock-frequency property on clint, so we need to fall back on the timebase-frequency property. Perhaps in the future we can get a clock-frequency property added to the qemu dtb. Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller. RISCV_SYSCON_CLINT is retained for this purpose. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
generated by cgit v1.1 at 2024-10-28 22:43:38 +0000