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| author | Tianrui Wei <tianrui-wei@outlook.com> | 2021-07-01 12:54:19 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-07-06 13:50:56 +0800 |
| commit | 8a44fe69439438797b93b2e7dd70e1a8fad31519 (patch) | |
| tree | 327e92caeef61a85ca5c9fc1824673764736d59a /arch/riscv/Kconfig | |
| parent | fe01f41d57b79d9ca94604503a25e55175744d42 (diff) | |
| download | u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.zip u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.tar.gz u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.tar.bz2 | |
board: riscv: add openpiton-riscv64 SoC support
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b3d7fd8..4b0c3df 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" +config TARGET_OPENPITON_RISCV64 + bool "Support RISC-V cores on OpenPiton SoC" + endchoice config SYS_ICACHE_OFF @@ -60,6 +63,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below |