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| author | Zong Li <zong.li@sifive.com> | 2021-09-01 15:01:41 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-09-07 10:34:29 +0800 |
| commit | 213ed175b0a97313982c8341c34e48f0ea59b60e (patch) | |
| tree | 6102386aeb7f61de9ec90cb49b4ff1ef9274e247 /arch/riscv/Kconfig | |
| parent | 4d4222d07432faffe3a0fe35c483e116a28eb217 (diff) | |
| download | u-boot-213ed175b0a97313982c8341c34e48f0ea59b60e.zip u-boot-213ed175b0a97313982c8341c34e48f0ea59b60e.tar.gz u-boot-213ed175b0a97313982c8341c34e48f0ea59b60e.tar.bz2 | |
riscv: lib: implement enable_caches for sifive cache
The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.
In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3df..ec651fe 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config SIFIVE_CACHE + bool + help + This enables the operations to configure SiFive cache + config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE |