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path: root/arch/riscv/Kconfig
AgeCommit message (Expand)AuthorFilesLines
2024-05-14andes: Unify naming policy for Andes related sourceLeo Yu-Chi Liang1-2/+2
2024-04-09riscv: Move virtio scan to board_late_init()Ɓukasz Stelmach1-0/+1
2024-04-09riscv: cpu: cv1800b: Add support for cv1800b SoCKongyang Liu1-0/+1
2024-04-09riscv: add backtrace supportBen Dooks1-0/+20
2024-03-13Kconfig: move CONFIG_32/64BIT to arch/KconfigDan Carpenter1-6/+0
2024-01-31riscv: sophgo: milkv_duo: initial support addedKongyang Liu1-0/+4
2023-12-18riscv: Add support for AMD/Xilinx MicroBlaze VMichal Simek1-0/+4
2023-11-02riscv: Sort target configs alphabeticallySamuel Holland1-9/+9
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek1-1/+0
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin1-0/+91
2023-10-19riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbolRandolph1-0/+8
2023-10-04configs: andes: add vender prefix for target nameRandolph1-2/+2
2023-10-04riscv: enable CONFIG_DEBUG_UART by defaultHeinrich Schuchardt1-0/+1
2023-09-26riscv: set fdtfile on VisionFive 2Heinrich Schuchardt1-0/+1
2023-08-10riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USEShengyu Qu1-0/+8
2023-07-12riscv: t-head: licheepi4a: initial support addedYixun Lan1-0/+5
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng1-4/+4
2023-07-12riscv: clint: Update the sifive clint ipi driver to support aclintBin Meng1-0/+4
2023-04-20board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang1-0/+5
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang1-4/+4
2022-11-15riscv: clarify meaning of CONFIG_SBI_V02Heinrich Schuchardt1-7/+7
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin1-3/+3
2022-10-20riscv: support building double-float modulesHeinrich Schuchardt1-0/+15
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen1-0/+7
2022-09-26spl: introduce SPL_XIP to configNikita Shubin1-0/+7
2022-04-06riscv: alloc space exhaustedHeinrich Schuchardt1-3/+0
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini1-0/+5
2021-09-07riscv: lib: implement enable_caches for sifive cacheZong Li1-0/+5
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek1-2/+0
2021-08-31Finish converting CONFIG_SYS_CACHELINE_SIZE to KconfigTom Rini1-0/+2
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei1-0/+4
2021-05-31board: sifive: add HiFive Unmatched board supportGreen Wan1-0/+4
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan1-0/+1
2021-05-17riscv: Group assembly optimized implementation of memory routines into a submenuBin Meng1-0/+4
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng1-1/+8
2021-04-08riscv: assembler versions of memcpy, memmove, memsetHeinrich Schuchardt1-0/+78
2021-04-08riscv: sifive: Rename fu540 board to unleashedBin Meng1-3/+3
2021-01-18riscv: Add DMA 64-bit address supportPadmarao Begari1-0/+4
2020-10-26riscv: Move Andes PLMT driver to drivers/timerSean Anderson1-7/+0
2020-10-26riscv: Only enable OF_BOARD_FIXUP for S-ModeSean Anderson1-1/+1
2020-09-30riscv: Rework Sifive CLINT as UCLASS_TIMER driverSean Anderson1-4/+0
2020-09-30riscv: Rework Andes PLMT as a UCLASS_TIMER driverSean Anderson1-4/+0
2020-09-30riscv: Rework riscv timer driver to only support S-modeSean Anderson1-8/+0
2020-07-06Merge branch 'next'Tom Rini1-0/+14
2020-07-02riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATEBin Meng1-0/+3
2020-07-01riscv: Add Sipeed Maix supportSean Anderson1-0/+4
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson1-0/+10
2020-06-04riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel1-0/+1
2020-04-23riscv: Make SBI v0.2 the default SBI versionBin Meng1-1/+1
2020-04-23riscv: Add Kconfig option for SBI v0.2Bin Meng1-1/+19