diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2022-10-25 23:03:50 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-11-03 13:27:56 +0800 |
| commit | a5dfa3b8a0f7ad555495bad1386613d2de4ba619 (patch) | |
| tree | 74a91e18cd008f381c12d615587912630530bed3 /arch/riscv/Kconfig | |
| parent | c8d9ff634fc429db5acf2f5386ea937f0fef1ae7 (diff) | |
| download | u-boot-a5dfa3b8a0f7ad555495bad1386613d2de4ba619.zip u-boot-a5dfa3b8a0f7ad555495bad1386613d2de4ba619.tar.gz u-boot-a5dfa3b8a0f7ad555495bad1386613d2de4ba619.tar.bz2 | |
riscv: Rename Andes PLIC to PLICSW
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8f95781..4d64e9b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -199,7 +199,7 @@ config SIFIVE_CACHE help This enables the operations to configure SiFive cache -config ANDES_PLIC +config ANDES_PLICSW bool depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP @@ -207,8 +207,8 @@ config ANDES_PLIC select SPL_REGMAP if SPL select SPL_SYSCON if SPL help - The Andes PLIC block holds memory-mapped claim and pending registers - associated with software interrupt. + The Andes PLICSW block holds memory-mapped claim and pending + registers associated with software interrupt. config SMP bool "Symmetric Multi-Processing" |