aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
AgeCommit message (Expand)AuthorFilesLines
46 hours[RISCV] Relax one of the zexti8 in the PACKH+PACK(W)/SLLI patterns. (#152384)Craig Topper1-7/+15
2 days[RISCV] Add packw+packh isel pattern for unaligned loads on RV64. (#152159)Craig Topper1-0/+21
3 days[RISCV] Simplify one of the RV32 PACK isel patterns. (#152045)Craig Topper1-6/+8
2025-07-09[RISCV] Add Commutable flag to XNOR. (#147654)Craig Topper1-1/+1
2025-07-08[RISCV] Select disjoint_or+not as xnor. (#147636)Craig Topper1-1/+2
2025-06-10[RISCV] Select (add/or C, x) -> (add.uw C|0xffffffff00000000, x) (#143375)Piotr Fusik1-0/+4
2025-05-12[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)Jim Lin1-43/+89
2025-05-09[RISCV] TableGen-erate RISC-V SDNodes (#138381)Sam Elliott1-13/+26
2025-02-15[RISCV] Support Zb*/P Shared Instructions (#127160)realqhc1-11/+15
2024-12-19[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)Piotr Fusik1-0/+6
2024-12-12[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to thei...Craig Topper1-0/+13
2024-12-10[RISCV][GISEl] Simplify GISelPredicateCode for binop_with_non_imm12. NFCCraig Topper1-2/+0
2024-11-18[RISCV] Use the OperandTransform field of a couple PatLeafs to simplify isel ...Craig Topper1-14/+14
2024-11-18[RISCV] Use getSignedTargetConstant. NFCCraig Topper1-6/+6
2024-11-13[RISCV] Add XLenVT casts in isel patterns that output 2 GPR instructions.Craig Topper1-2/+3
2024-10-06[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to A...Craig Topper1-23/+17
2024-10-05[RISCV] Unify RVBShift_ri and RVBShiftW_ri with Shift_ri and ShiftW_ri. NFC (...Craig Topper1-13/+6
2024-10-05[RISCV] Give ZEXT_H_RV32 and ZEXT_H_RV64 R-type format to match PACK. NFCCraig Topper1-2/+10
2024-10-01[RISCV] Add pattern for PACK/PACKH in common misaligned load case (#110644)Alex Bradbury1-1/+12
2024-08-19[RISCV] Improve BCLRITwoBitsMaskHigh SDNodeXForm. NFCCraig Topper1-2/+2
2024-08-17[RISCV] Remove unused tablegen classes from unratified Zbp instructions. NFCCraig Topper1-24/+0
2024-08-17[RISCV] Use getAllOnesConstant/getSignedConstant.Craig Topper1-6/+6
2024-08-12[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGIS...Craig Topper1-101/+0
2024-06-27[RISCV] Rework zext.h handling for Zbkb again. (#96957)Craig Topper1-9/+29
2024-06-27[RISCV] Support zext.h mnemonic with Zbkb. (#96821)Craig Topper1-12/+9
2024-05-08[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966)Philip Reames1-74/+0
2024-04-23[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789)Philip Reames1-0/+2
2024-04-23Reapply "[RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (...Philip Reames1-37/+22
2024-04-22Revert "[RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (#...Philip Reames1-22/+37
2024-04-22[RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (#89263)Philip Reames1-37/+22
2024-03-28[RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001)Philip Reames1-25/+25
2024-03-28[RISCV] Add add_like PatFrags to reduce number of required patterns [nfc] (#8...Philip Reames1-9/+3
2024-03-14[RISCV] Add sched classes for Zbb integer min max instructionsMichael Maitland1-4/+4
2024-02-08[RISCV] Add casts to isel patterns that produce more than 1 instruction.Craig Topper1-48/+51
2024-02-08[RISCV] Use replace XLenVT with i64 in some isel patterns that are only used ...Craig Topper1-8/+8
2024-02-04[RISCV] Add i32 zext.h pattern for -riscv-experimental-rv64-legal-i32.Craig Topper1-0/+2
2023-11-21[RISCV] Add more Zbs patterns for -riscv-experimental-rv64-legal-i32.Craig Topper1-0/+5
2023-11-16[RISCV] Use bset+addi for (not (sll -1, X)).Craig Topper1-0/+2
2023-11-11[RISCV] Add more packh patterns.Craig Topper1-0/+7
2023-11-11[RISCV] Add packw/packh patterns for -riscv-experimental-rv64-legal-i32Craig Topper1-0/+12
2023-11-11[RISCV] Add isel pattern to turn (or (zext X), Y) into add.uw when X and Y ar...Craig Topper1-0/+3
2023-11-11[RISCV] Add an slli.uw pattern using zext for -riscv-experimental-rv64-legal-i32Craig Topper1-1/+4
2023-11-10[RISCV][GISel] Promote s32 constant shift amounts to s64 on RV64.Craig Topper1-0/+6
2023-11-10[RISCV] Add an add.uw pattern using zext for -riscv-experimental-rv64-legal-i...Craig Topper1-0/+2
2023-11-09[RISCV] Disable Zbs special case in performTRUNCATECombine with -riscv-experi...Craig Topper1-0/+2
2023-11-09[RISCV] Add BSET/BCLR/BINV/BEXT patterns for riscv-experimental-rv64-legal-i32.Craig Topper1-0/+14
2023-11-01[RISCV] Add RV64 i32 patterns for bseti/bclri/binvi.Craig Topper1-0/+16
2023-11-01[RISCV] Don't promote i32 and/or/xor with -riscv-experimental-rv64-legal-i32.Craig Topper1-0/+4
2023-11-01[RISCV] Add experimental support for making i32 a legal type on RV64 in Selec...Craig Topper1-0/+26
2023-10-24[RISCV][GISel] Add ISel support for SHXADD_UW and SLLI.UW (#69972)Min-Yih Hsu1-19/+10
generated by cgit v1.1 at 2025-08-08 23:06:26 +0000