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AgeCommit message (Expand)AuthorFilesLines
2 hours[SPIR-V] Don't consider a function be a builtin just by checking name (#182776)Dmitry Sidorov2-190/+206
2 hours[SelectionDAG] Add expansion for llvm.convert.from.arbitrary.fp (#179318)Dmitry Sidorov10-9/+346
2 hours[DSE] Handle provenance when eliminating tautological assignmentsAntonio Frighetto1-0/+7
2 hours[InstCombine] make `foldBinOpIntoSelectOrPhi` fold on all operands (#183692)Kiva1-10/+12
3 hours[WebAssembly] Print type signature and table for call_indirect (#179120)hanbeom2-6/+13
3 hours[Loads] Allow replacement of null with ptr in `canReplacePointersIfEqual`Antonio Frighetto1-2/+5
4 hours[InstCombine] Don't strip leading zero index for overaligned vector GEP (#184...Nikita Popov1-1/+2
4 hours[VPlan] Add const to VPPredicator methods. nfc (#184359)Mel Chen1-8/+9
4 hours[DA] Remove consistent flag from Dependence class (#181608)Ryotaro Kasuga1-18/+1
4 hours[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)Steffen Larsen1-95/+82
5 hours[X86][APX] Add a few pseudo opcodes support EGPR (#184550)Phoebe Wang1-8/+29
5 hours[MC] Fuse relaxation and layout into a single forward pass (#184544)Fangrui Song1-42/+60
6 hours[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)Luke Lau4-34/+52
6 hours[GVN] Fix crash when svcount is used with globals-aa (#184347)Madhur Amilkanthwar1-1/+1
6 hours[RISCV] Remove OperandType OPERAND_SIMM10_UNSIGNED. Rename OPERAND_SIMM8_UNSI...Craig Topper3-6/+4
8 hours[RISCV][GISel] Replace buildInstr with BuildMI (#183714)Jianjian Guan1-142/+213
10 hours[TargetLowering][PowerPC] Don't unroll vector CLMUL when MUL is not supported...Craig Topper1-4/+0
11 hours[NFC] Don't replicate hasKernelCallingConv. (#184464)Alexey Bader1-7/+1
12 hours[LoopUnrollPass] Add `const` to parameters in `computeUnrollCount` (NFC) (#18...Justin Fargnoli1-2/+3
12 hours[WebAssembly] Use MVT::i32 instead of i1 in performAnyAllCombine (#183866)Derek Schuff1-9/+8
13 hours[X86] support reserve r8~r15 on X86_64 (#180242)zhouguangyuan07186-1/+48
14 hours[AMDGPU] Add suffix _d4 to tensor load/store with 4 groups D#, NFC (#184176)Changpeng Fang6-22/+22
15 hours[AMDGPU][SIInsertWaitcnts][NFC] Call applyWaitcnt() in a loop (#184426)vporpo1-10/+2
15 hours[AMDGPU] Add dereferenceable retAttr to a call to llvm.amdgcn.implicitarg.ptr...Yoonseo Choi2-1/+25
15 hours[X86] getFauxShuffleMask - add ISD::ROTL/ROTR handling (#184417)Simon Pilgrim1-0/+31
16 hours[RISCV] Fix type inference ambiguity in SwapSysReg pattern (#184305)lihengda861-source1-1/+1
16 hours[HLSL][SPIRV] Fix `faceforward` pattern matcher logic (#183630)Kaitlin Peng1-5/+5
16 hours[VPlan] Use bitfield to store Cmp predicates and GEP wrap flags. (NFC) (#181571)Florian Hahn2-31/+47
16 hours[Analysis][DXILResource] Correct bound computation (#184198)Finn Plummer1-4/+7
17 hours[NFC] Refactor the SelectionDAG::getMemcmp etc with a existing helper funct...zhijian lin1-56/+6
17 hours[RISCV] Promote i8/i16/i32 scalable vector CLMUL to i64 CLMUL with Zvbc. (#18...Craig Topper1-2/+25
17 hours[WebAssembly][FastISel] Call materializeLoadStoreOperands in load fold (#184203)hanbeom1-16/+19
17 hours[AArch64] Fix relative vtable PLT/GOTPCREL specifiers to use MCSpecifierExpr ...Fangrui Song2-9/+7
18 hours[VPlan][NFC] Remove unnecessary explicit copy constructors (#183863)calebwat1-9/+0
19 hours[DirectX][ResourceAccess] Resolve resource handles at access (#182106)Finn Plummer1-4/+247
19 hours[AArch64] Add basic NPM support for LoadStoreOptimizer. (#184090)David Green4-23/+86
19 hours[Thumb2] Use BXAUT instruction if available (#183056)walkerkd3-3/+17
20 hoursReapply "[SPIRV][NFCI] Use unordered data structures for SPIR-V extensions (#...Nick Sarnie7-197/+179
20 hoursFix `assignValueToReg` function's argument (#184354)Shoreshen1-2/+4
20 hours[NFC][AArch64] isPureCmp is a duplicate of canAdjustCmp, so remove the duplic...SiliconA-Z1-19/+1
21 hours[AMDGPU] Generate more swaps (#184164)LU-JOHN1-54/+64
21 hours[AArch64] Fix type mismatch in bitconvert + vec_extract patterns (#183549)Lukacma1-2/+2
21 hours[SPIRV] Don't emit service function basic block names (#184206)Nick Sarnie1-0/+4
22 hours[VPlan] Preserve IsSingleScalar for sunken predicated stores. (#184329)Florian Hahn1-5/+7
23 hoursRevert "Avoid maxnum(sNaN, x) optimizations / folds (#170181)" (#184125)Lewis Crawford5-30/+22
23 hours[DAG] isKnownNeverZero - add ISD::OR DemandedElts handling (#183228)Shekhar1-2/+2
23 hours[AArch64] Limit support to f32 and f64 in performSelectCombine (#184315)David Green1-1/+1
24 hours[RISCV] Remove VL != 1 restriction in RISCVVLOptimizer (#184298)Luke Lau1-7/+0
25 hours[AArch64] Add vector expansion support for ISD::FCBRT when using ArmPL (#183750)David Sherwood5-20/+89
25 hours[DAG] isKnownNeverZero - add ISD::UADDSAT/UMAX/UMIN DemandedElts handling and...Shekhar1-5/+7
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