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36 min.[NewPM] Port x86-global-base-reg (#180119)HEADmainKyungtak Woo8-109/+161
102 min.[RISCV] Remove redundant czero in multi-word comparisons (#180485)Craig Topper3-74/+66
3 hours[DebugInfo] Fix an assertion in DWARFTypePrinter (#178986)Peter Rong2-3284/+3408
4 hoursFix LLDB data formatter for llvm::Expected<T> with non-reference types (#179294)jeffreytan811-2/+15
5 hours[RISCV] Rename FeatureEnableSelectOptimize to TuneEnableSelectOptimize (#180496)Pengcheng Wang1-1/+1
5 hoursAMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)vangthao953-181/+420
5 hoursLowerTypeTests: Optimize two-phase check used by llvm.cond.loop.Peter Collingbourne2-5/+65
6 hours[AMDGPU][SIInsertWaitcnt][NFC] Access Waitcnt elements using InstCounterType ...vporpo3-81/+110
6 hours[RISCV] Generate 8alt/16alt version error message for zvfofp8min (#180450)Jim Lin3-0/+12
6 hours[DebugInfo] Update test to sync with cross-project-tests (#180655)Peter Rong1-5362/+5490
7 hours[SPIRV] Add handling for `uinc_wrap` and `udec_wrap` atomics (#179114)Lleu Yang6-1/+118
7 hoursRevert "[msan] Switch switch() from strict handling to (icmp eq)-style handli...Andrew Lazarev2-61/+5
8 hours[SPIR-V] Emit ceil(Bitwidth / 32) words during OpConstant creation (#180218)Dmitry Sidorov2-7/+39
8 hours[win][aarch64] The Windows Control Flow Guard Check function also preserves X...Daniel Paoliello2-23/+63
8 hours[LV] Add FindLast tests where IV-based expression could be sunk. (NFC)Florian Hahn1-0/+934
8 hours[RISCV] Add missing instruction tests to rv64p-valid.s. NFC (#180316)Craig Topper1-0/+12
8 hours[VPlan] Auto-generate CHECKs in some VPlan printing tests.Florian Hahn4-150/+251
8 hours[LV] Add additional tests for reductions with intermediate stores. (NFC)Florian Hahn2-3/+160
9 hours[RISCV] Combine shuffle of shuffles to a single shuffle (#178095)Ryan Buchner3-7/+499
9 hours[SPIRV] Implement lowering for HLSL Texture2D sampling intrinsics (#179312)Steven Perron16-48/+860
9 hours[VPlan] Simplify single-entry VPWidenPHIRecipe.Florian Hahn8-28/+19
10 hours[SPGO] Use std::hash instead of MD5 to avoid run time regression in llvm-prof...HighW4y2H3ll1-1/+7
10 hours[AArch64] Inline asm v0-v31 are scalar when having less than 64-bit capacity ...Alexey Merzlyakov2-4/+188
11 hours[NFC][LLVM][IPO] Remove pass initialization from pass constructors (#180584)Rahul Joshi8-17/+10
11 hours[TargetLowering] Avoid creating a VTList until we know we need it. NFC (#180599)Craig Topper1-2/+2
11 hours[Hexagon] Fix encoding of packets with fixups followed by alignment (#179168)Brian Cain2-0/+56
12 hours[ForceFunctionAttrs] Fix handling of `alwaysinline` and `noinline` attributes...Justin Fargnoli2-11/+48
12 hours[AMDGPU] Enable sinking of free vector ops that will be folded into their use...Gheorghe-Teodor Bercea3-13/+237
13 hours[Profile] Enable binary profile correlation for Mach-O binaries (#179937)Marina Taylor2-5/+40
13 hours[SPARC] Add TTI implementation for getPopcntSupport (#178843)Koakuma7-0/+409
13 hoursRevert "[NFC][LLVM][IPO] Remove pass initialization from pass constructors" (...Rahul Joshi7-9/+17
14 hours[llubi] Add initial support for llubi (#180022)Yingwei Zheng15-0/+1279
14 hours[AArch64] Add support for B and H loads/stores in LoadStoreOptimizer (#180535)John Brawn3-0/+274
14 hoursAMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sffbh (#180099)vangthao952-19/+33
14 hoursAMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)vangthao955-0/+1776
14 hours[MIParser] - Add support for MMRAs (#180320)Ryan Mitchell5-2/+97
15 hours[NFC][LLVM][IPO] Remove pass initialization from pass constructors (#180154)Rahul Joshi7-17/+9
15 hours[RISCV] Combine ADDD+WMULSU to WMACCSU (#180454)Craig Topper4-15/+73
15 hours[gn build] Port da0ad392ffc6LLVM GN Syncbot1-0/+1
15 hours[X86] Fold expand(splat,passthrough,mask) -> select(splat,passthrough,mask) (...Simon Pilgrim2-12/+13
16 hours[InstCombine] Support minimumnum/maximumnum (#180529)Nikita Popov3-2/+844
16 hours[SPIR-V] initial support for @llvm.structured.gep (#178668)Nathan Gauër9-17/+478
16 hours[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)Anshil Gandhi9-46/+501
16 hoursReland "[LoopVectorize] Support vectorization of overflow intrinsics" (#180526)Vishruth Thimmaiah5-27/+572
16 hours[CodeGen][NFC] Update a comment. (#180531)Mikhail Gudim1-1/+1
16 hours[llvm][DebugInfo] Avoid attaching retained nodes to unrelated subprograms in ...Vladislav Dzhidzhoev2-4/+64
16 hours[OpenMP][flang] Enabling support for Allocate clause in DO construct (#180172)ShashwathiNavada1-0/+2
16 hours[IR] Update docstring for stripAndAccumulateConstantOffset (#180365)Aiden Grossman1-3/+4
16 hours[IVDesc] Check loop-preheader for loop-legality when pass-remarks enabled (#1...hanbeom2-2/+30
17 hours[AMDGPU] Fix instruction size for 64-bit literal constant operands (#180387)Shilei Tian2-3/+18
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