aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target
AgeCommit message (Expand)AuthorFilesLines
13 hours[RISCV] Fix typo in comment. NFCCraig Topper1-1/+1
16 hoursPPC: Fix regression for 32-bit ppc with 64-bit support (#159893)Matt Arsenault1-1/+1
18 hoursX86: Elide use of RegClassByHwMode in some ptr_rc_tailcall uses (#159874)Matt Arsenault2-4/+4
18 hours[M68k] Remove STI from M68kAsmParser (#159827)Sergei Barannikov1-3/+2
20 hours[RISCV] Update comments in RISCVMatInt to reflect we don't always use ADDIW a...Craig Topper1-14/+15
22 hoursRevert "[PowerPC] clean unused PPC target feature FeatureBPERMD" (#159837)Sergei Barannikov1-1/+4
24 hours[AArch64] Clean up the formatting of some bitconvert patterns. NFCDavid Green1-145/+144
24 hours[ARM] Replace ABS and tABS machine nodes with custom lowering (#156717)AZero138-151/+60
25 hours[PowerPC] clean unused PPC target feature FeatureBPERMD (#159782)zhijian lin1-4/+1
25 hours[ARM] Verify that disassembled instruction is correct (#157360)Sergei Barannikov1-41/+27
25 hours[RISCV] Use MutableArrayRef instead of SmallVectorImpl&. NFC (#159651)Craig Topper1-2/+2
25 hours[AArch64] Remove post-decoding instruction mutations (#156364)Sergei Barannikov6-78/+153
25 hours[WebAssembly] Require tags for Wasm EH and Wasm SJLJ to be defined externally...Sam Clegg1-7/+0
26 hours[AMDGPU]: Unpack packed instructions overlapped by MFMAs post-RA scheduling (...Akash Dutta3-5/+398
26 hours[RISCV] Re-work how VWADD_W_VL and similar _W_VL nodes are handled in combine...Craig Topper1-37/+49
26 hours[RISCV] Fix build after e747223c03e16d02cd0dc6f8eedb5c825a7366c1Michael Liao1-2/+2
26 hours[NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (#159619)Brandon Wu5-60/+66
27 hoursPPC: Replace PointerLikeRegClass with RegClassByHwMode (#158777)Matt Arsenault4-24/+26
28 hours[PowerPC] Fix vector extend result types in BUILD_VECTOR lowering (#159398)RolandF771-1/+5
28 hours[PowerPC] using milicode call for strlen instead of lib call (#153600)zhijian lin4-3/+12
28 hoursMips: Switch to RegClassByHwMode (#158273)Matt Arsenault8-48/+80
29 hoursX86: Switch to RegClassByHwMode (#158274)Matt Arsenault7-41/+55
29 hours[CodeGen][NewPM] Port `ReachingDefAnalysis` to new pass manager. (#159572)Mikhail Gudim4-64/+62
29 hoursX86: Avoid using isArch64Bit for 64-bit checks (#157412)Matt Arsenault8-30/+29
30 hoursSPARC: Use RegClassByHwMode instead of PointerLikeRegClass (#158271)Matt Arsenault2-10/+19
30 hours[LLVM][CodeGen] Update PPCFastISel::SelectRet for ConstantInt based vectors. ...Paul Walker1-1/+2
31 hours[X86] Fold X * 1 + Z --> X + Z for VPMADD52L (#158516)Hongyu Chen1-1/+23
31 hoursCodeGen: Add RegisterClass by HwMode (#158269)Matt Arsenault5-7/+12
31 hours[X86] Allow all legal integers to optimize smin with 0 (#151893)AZero131-1/+1
33 hoursRISC-V: builtins support for MIPS RV64 P8700 execution control .UmeshKalappa2-1/+8
33 hours[SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD transforms (#146074)Fabian Ritter2-49/+13
34 hours[AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (#145330)Fabian Ritter2-6/+7
34 hours[RISCV] Implement MC support for Zvfofp8min extension (#157014)Jim Lin4-4/+45
36 hours[RISCV][GISel] Support select vx, vf form rvv intrinsics (#157398)Jianjian Guan4-2/+51
36 hours[LoongArch] Simplily fix extractelement on LA32 (#159564)ZhaoQi3-21/+23
38 hours[RISCV] Use Subtarget member variable instead of getting it from MachineFunct...Craig Topper1-9/+7
38 hours[RISCV] Ignore debug instructions in RISCVVLOptimizer (#159616)Luke Lau1-1/+2
38 hoursRevert "[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embe...Florian Mayer2-80/+0
39 hours[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embed in Mem...Hank Chang2-0/+80
39 hours[RISC-V] Add P-ext MC Support for Remaining Pair Operations (#159247)Qihan Cai1-0/+258
41 hours[LoongArch] Add generation support for `[x]vnori.b` (#158772)ZhaoQi2-2/+6
41 hoursAMDGPU: Remove unnecessary AGPR legalize logic (#159491)Matt Arsenault1-13/+0
42 hours[RISCV] Use bseti 31 for (or X, -2147483648) when upper 32 bits aren't used. ...Craig Topper1-0/+13
42 hours[RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147)Sam Elliott3-81/+105
43 hours[AMDGPU] gfx1251 VOP3 dpp support (#159654)Stanislav Mekhanoshin3-51/+92
44 hours[AMDGPU] gfx1251 VOP2 dpp support (#159641)Stanislav Mekhanoshin1-34/+45
44 hours[RISCV] Pass SDValue by value. NFCCraig Topper1-4/+4
46 hours[AMDGPU] gfx1251 VOP1 dpp support (#159637)Stanislav Mekhanoshin1-22/+43
46 hours[RISCV] Update the vector integer division cycle in SiFive7 scheduling model ...Min-Yih Hsu1-2/+5
46 hours[RISCV] Update floating point load latency in SiFive7 scheduling model (#159462)Min-Yih Hsu1-10/+8
generated by cgit v1.1 at 2025-09-20 18:14:04 +0000