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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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2025-06-18[PowerPC] Add code to spill and restore DMRp registers (#142443)Lei Huang1-52/+55
2025-06-12[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#143953)Lei Huang1-46/+42
2025-06-12Revert "[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spil… (#14...Lei Huang1-43/+50
2025-06-12[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#142220)Lei Huang1-50/+43
2025-06-02[PowerPC] Spill and restore DMR register (#141530)Lei Huang1-0/+95
2025-05-22[PowerPC][NFC] clean up if-else block in PPCRegisterInfo.cpp (#140084)Lei Huang1-33/+42
2025-04-04[PowerPC] Fix instruction name for dmr insert (#134301)Lei Huang1-1/+1
2025-04-03[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#133155)zhijian lin1-0/+7
2025-02-19Revert "[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (...David Tenty1-7/+0
2025-02-13[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#116984)zhijian lin1-0/+7
2025-01-18[CodeGen] Use Register/MCRegister::isPhysical. NFCCraig Topper1-1/+1
2024-12-12CodeGen: Eliminate dynamic relocations in the register superclass tables. (#1...Owen Anderson1-7/+9
2024-12-11Revert "CodeGen: Eliminate dynamic relocations in the register superclass tab...Owen Anderson1-9/+7
2024-12-11CodeGen: Eliminate dynamic relocations in the register superclass tables. (#1...Owen Anderson1-7/+9
2024-11-14[PowerPC] Remove unused includes (NFC) (#116163)Kazu Hirata1-2/+0
2024-11-04[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)zhijian lin1-18/+14
2024-05-29[PowerPC] option `-msoft-float` should not block the PC-relative address inst...zhijian lin1-1/+1
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang1-6/+6
2024-01-26[NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate...Shengchen Kan1-1/+1
2023-01-13[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegist...Craig Topper1-1/+1
2022-11-22[PowerPC] Add handling for WACC register spilling.Stefan Pintilie1-0/+97
2022-11-18PEI should be able to use backward walk in replaceFrameIndicesBackward.Alexander Timofeev1-14/+18
2022-10-13[PowerPC] Stash GPR to VSR if emergency spill slot is not reachableNemanja Ivanovic1-2/+25
2022-10-09[PowerPC] Add vector pair calling convention for AIXTing Wang1-1/+15
2022-10-04[PowerPC] Fix the register allocation hints for ACC registers.Stefan Pintilie1-4/+12
2022-09-03[llvm] Use range-based for loops (NFC)Kazu Hirata1-7/+6
2022-08-10[PowerPC] Don't use the S30 and S31 regs for the pic codeUmesh Kalappa1-3/+9
2022-06-20[PowerPC] Disable automatic generation of STXVPNemanja Ivanovic1-6/+69
2022-06-16[PowerPC] Fix LQ-STQ instructions to use correct offset and baseAhsan Saghir1-1/+26
2022-06-06[PowerPC] Support huge frame size for PPC64Kai Luo1-6/+9
2022-03-16[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated ...Shengchen Kan1-1/+1
2022-03-16Cleanup codegen includesserge-sans-paille1-0/+1
2022-03-15[PowerPC][P10] Add Vector pair calling conventionStefan Pintilie1-13/+38
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-1/+0
2022-03-10Cleanup codegen includesserge-sans-paille1-0/+1
2022-01-24[PowerPC] Emit warning when SP is clobbered by asmQuinn Pham1-0/+12
2022-01-19[NFC] Use Register instead of unsignedJim Lin1-1/+1
2021-09-14[PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implem...Amy Kwan1-2/+19
2021-07-29[PowerPC] Fix issue where hint was providing the incorrect regsiter class.Stefan Pintilie1-1/+3
2021-07-20[PowerPC] Inefficient register allocation of ACC registers results in many co...Stefan Pintilie1-0/+56
2021-06-15[PowerPC] Fix spilling of paired VSX registersNemanja Ivanovic1-0/+22
2021-06-15[PowerPC] Export 16 byte load-store instructionsKai Luo1-0/+61
2021-06-11[PowerPC] Relax register superclasses for paired memopsQiu Chaofan1-7/+21
2021-05-13[PowerPC] Add ROP Protection to prologue and epilogueStefan Pintilie1-0/+10
2021-05-10[PowerPC] Spilling to registers does not require frame index scavengingStefan Pintilie1-4/+24
2021-05-03[AIX] Remove unused vector registers from allocation order in the default Alt...Zarko Todorovski1-4/+19
2021-03-31[PowerPC] [MLICM] Enable hoisting of caller preserved registers on AIXShimin Cui1-9/+7
2021-03-30[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functionsTomas Matheson1-1/+1
2021-03-05[PowerPC][AIX] Enable the default AltiVec ABI on AIXZarko Todorovski1-14/+40
2021-03-03[PowerPC] Allow spilling GPR to VSR on AIXQiu Chaofan1-1/+1
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