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2025-06-18[PowerPC] Add code to spill and restore DMRp registers (#142443)Lei Huang1-52/+55
2025-06-12[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#143953)Lei Huang1-46/+42
Simpliy handling for spilling of acc reg with stx by removing explicit register arithmetic and clean up code gen for register mapping used in stxvp spilling. Relanding: https://github.com/llvm/llvm-project/pull/142220
2025-06-12Revert "[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spil… ↵Lei Huang1-43/+50
(#143948) …ling (#142220)" This reverts commit edf636afe405ff90da7bf1834aa334bd52bc861e. checked in wrong branch.
2025-06-12[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#142220)Lei Huang1-50/+43
Remove explicit register arithmetic from spilling ACC and STXVP code.
2025-06-02[PowerPC] Spill and restore DMR register (#141530)Lei Huang1-0/+95
Add spilling and restoring of DMR registers.
2025-05-22[PowerPC][NFC] clean up if-else block in PPCRegisterInfo.cpp (#140084)Lei Huang1-33/+42
Move all if-else conditions into a switch stmt for handling spills.
2025-04-04[PowerPC] Fix instruction name for dmr insert (#134301)Lei Huang1-1/+1
2025-04-03[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#133155)zhijian lin1-0/+7
ISD::ADDC, ISD::ADDE, ISD::SUBC and ISD::SUBE are being deprecated, using ISD::UADDO_CARRY,ISD::USUBO_CARRY instead. Lowering the UADDO, UADDO_CARRY, USUBO, USUBO_CARRY in the patch.
2025-02-19Revert "[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE ↵David Tenty1-7/+0
(#116984)" This reverts commit 7763119c6eb0976e4836f81c9876c49a36d46d73 (leaving the modifications from 03cb46d248b08)..
2025-02-13[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#116984)zhijian lin1-0/+7
ISD::ADDC, ISD::ADDE, ISD::SUBC and ISD::SUBE are being deprecated, using ISD::UADDO_CARRY,ISD::USUBO_CARRY instead. Lowering the UADDO, UADDO_CARRY, USUBO, USUBO_CARRY in the patch.
2025-01-18[CodeGen] Use Register/MCRegister::isPhysical. NFCCraig Topper1-1/+1
2024-12-12CodeGen: Eliminate dynamic relocations in the register superclass tables. ↵Owen Anderson1-7/+9
(#119487) This reapplies #119122 with a fix for UBSAN errors in the X86 backend related to incrementing a nullptr.
2024-12-11Revert "CodeGen: Eliminate dynamic relocations in the register superclass ↵Owen Anderson1-9/+7
tables. (#119122)" Reverting due to UBSan failures in X86RegisterInfo::getLargestLegalSuperClass This reverts commit c4873819a98f59ce4e2664f94c73c2dfec3393f8.
2024-12-11CodeGen: Eliminate dynamic relocations in the register superclass tables. ↵Owen Anderson1-7/+9
(#119122)
2024-11-14[PowerPC] Remove unused includes (NFC) (#116163)Kazu Hirata1-2/+0
Identified with misc-include-cleaner.
2024-11-04[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)zhijian lin1-18/+14
This patch utilizes getReservedRegs() to find asm clobberable registers. And to make the result of getReservedRegs() accurate, this patch implements the todo, which is to make r2 allocatable on AIX for some leaf functions.
2024-05-29[PowerPC] option `-msoft-float` should not block the PC-relative address ↵zhijian lin1-1/+1
instruction (#92543) The Prefix instruction is introduced on PowerPC ISA3_1. In the PR, 1. The `FeaturePrefixInstrs` do not imply the `FeatureP8Vector` ,`FeatureP9Vector` . 2. `FeaturePrefixInstrs` implies only the FeatureISA3_1. 3. For the prefix instructions `paddi` and `pli` , they have `Predicates = [PrefixInstrs] ` 4. For the prefix instructions `plfs` and `plfd`, they have `Predicates = [PrefixInstrs, HasFPU] ` 5. For the prefix instructions "plxv` , "plxssp` and `plxsd` , they have `Predicates = [PrefixInstrs, HasP10Vector]` Fixes #62372
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang1-6/+6
Fixes #82659 There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411. Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact. After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.
2024-01-26[NFC] Rename TargetInstrInfo::FoldImmediate to ↵Shengchen Kan1-1/+1
TargetInstrInfo::foldImmediate and simplify implementation for X86
2023-01-13[CodeGen][Target] Remove uses of ↵Craig Topper1-1/+1
Register::isPhysicalRegister/isVirtualRegister. NFC Use isPhysical/isVirtual methods.
2022-11-22[PowerPC] Add handling for WACC register spilling.Stefan Pintilie1-0/+97
This patch adds spilling for the new WACC registers. In order to get the spilling test to work the MMA instructions from Power 10 are now supported for Future CPU except that they are all using the new WACC registers instead of the ACC registers from Power 10. Reviewed By: amyk, saghir Differential Revision: https://reviews.llvm.org/D136728
2022-11-18PEI should be able to use backward walk in replaceFrameIndicesBackward.Alexander Timofeev1-14/+18
The backward register scavenger has correct register liveness information. PEI should leverage the backward register scavenger. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D137574
2022-10-13[PowerPC] Stash GPR to VSR if emergency spill slot is not reachableNemanja Ivanovic1-2/+25
When removing frame indices on PowerPC, we need to scavenge a GPR to materialize a large constant if the stack offset for the spill/reload cannot be reached by a D-Form instruction. However, in a perfect storm of conditions, we may not have GPR's available to scavenge, thereby requiring an emergency spill. If such an emergency spill also needs to be spilled to a location with a large offset, it would itself require register scavenging thereby creating an infinite loop. This patch detects when the scavenger cannot scavenge a register and the spill/reload is to a location with a large offset. It then stashes a GPR into a VSR so that it can use the GPR to materialize the constant (rather than scavenging a GPR). Fixes: https://github.com/llvm/llvm-project/issues/52894 Differential revision: https://reviews.llvm.org/D124841
2022-10-09[PowerPC] Add vector pair calling convention for AIXTing Wang1-1/+15
This is AIX part of update after https://reviews.llvm.org/D117225 Fixed the issue that AIX64 with vector pair enabled saw redundant spill/reload of callee saved vector registers. Based on original patch by: Kai Luo Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D133466
2022-10-04[PowerPC] Fix the register allocation hints for ACC registers.Stefan Pintilie1-4/+12
The allocation hints for copies of ACC registers assumed that we would only be copying between VSRp and UACC registers. In reality it is also possible to copy between UACC and ACC registers. This patch adds a new case for the ACC copy to fix that issue. Note that the test case added with this patch will hit an assert without the fix. Reviewed By: lei, amyk Differential Revision: https://reviews.llvm.org/D134501
2022-09-03[llvm] Use range-based for loops (NFC)Kazu Hirata1-7/+6
2022-08-10[PowerPC] Don't use the S30 and S31 regs for the pic codeUmesh Kalappa1-3/+9
These changes to address issue https://github.com/llvm/llvm-project/issues/55857. Since R30/S30 is used as pointer (32 bits) for GOT Table in the ppc32 ABI, remove it from the SPE callee save register when PIC is enabled. This prevents emitting the SPE load and store for S30 and S31 regs. Differential revision: https://reviews.llvm.org/D127495
2022-06-20[PowerPC] Disable automatic generation of STXVPNemanja Ivanovic1-6/+69
There are instances where using paired vector stores leads to significant performance degradation due to issues with store forwarding.To avoid falling into this trap with compiler - generated code, we will not emit these instructions unless the user requests them explicitly(with a builtin or by specifying the option). Reviewed By : lei, amyk, saghir Differential Revision: https://reviews.llvm.org/D127218
2022-06-16[PowerPC] Fix LQ-STQ instructions to use correct offset and baseAhsan Saghir1-1/+26
This patch fixes the load and store quadword instructions on PowerPC to use correct offset and base address. Reviewed By: #powerpc, nemanjai, lkail Differential Revision: https://reviews.llvm.org/D126807
2022-06-06[PowerPC] Support huge frame size for PPC64Kai Luo1-6/+9
Support allocation of huge stack frame(>2g) on PPC64. For ELFv2 ABI on Linux, quoted from the spec 2.2.3.1 General Stack Frame Requirements > There is no maximum stack frame size defined. On AIX, XL allows such huge frame. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D107886
2022-03-16[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated ↵Shengchen Kan1-1/+1
comments
2022-03-16Cleanup codegen includesserge-sans-paille1-0/+1
This is a (fixed) recommit of https://reviews.llvm.org/D121169 after: 1061034926 before: 1063332844 Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
2022-03-15[PowerPC][P10] Add Vector pair calling conventionStefan Pintilie1-13/+38
Add the calling convention for the vector pair registers. These registers overlap with the vector registers. Part of an original patch by: Lei Huang Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D117225
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-1/+0
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
2022-03-10Cleanup codegen includesserge-sans-paille1-0/+1
after: 1061034926 before: 1063332844 Differential Revision: https://reviews.llvm.org/D121169
2022-01-24[PowerPC] Emit warning when SP is clobbered by asmQuinn Pham1-0/+12
This patch emits a warning when the stack pointer register (`R1`) is found in the clobber list of an inline asm statement. Clobbering the stack pointer is not supported. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D112073
2022-01-19[NFC] Use Register instead of unsignedJim Lin1-1/+1
2021-09-14[PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store ↵Amy Kwan1-2/+19
Implementation This patch exploits the prefixed load and store instructions utilizing the refactored load/store implementation introduced in D93370. Prefixed load and store instructions are emitted whenever we are loading or storing a value with an offset that fits into a 34-bit signed immediate. Patterns for the prefixed load and stores are added in this patch, as well as the implementation that detects when we are loading and storing a value with an offset that fits in 34-bits. Differential Revision: https://reviews.llvm.org/D96075
2021-07-29[PowerPC] Fix issue where hint was providing the incorrect regsiter class.Stefan Pintilie1-1/+3
Regsier hints when copying to a UACC register do not always produce VSRp registers. This patch makes sure that we do not produce hints in cases where the subregsiter of the UACC is not a VSRp. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D107101
2021-07-20[PowerPC] Inefficient register allocation of ACC registers results in many ↵Stefan Pintilie1-0/+56
copies. ACC registers are a combination of four consecutive vector registers. If the vector registers are assigned first this often forces a number of copies to appear just before the ACC register is created. If the ACC register is assigned first then fewer copies are generated when the vector registers are assigned. This patch tries to force the register allocator to assign the ACC registers first and then the UACC registers and then the vector pair registers. It does this by changing the priority of the register classes. This patch also adds hints to help the register allocator assign UACC registers from known ACC registers and vector pair registers from known UACC registers. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D105854
2021-06-15[PowerPC] Fix spilling of paired VSX registersNemanja Ivanovic1-0/+22
We have added STXVP/LXVP for spilling and restoring the registers but we neglected to add FI elimination code for these. The result is that we end up producing impossible MachineInstr's that have register operands in place of immediates.
2021-06-15[PowerPC] Export 16 byte load-store instructionsKai Luo1-0/+61
Export `lq`, `stq`, `lqarx` and `stqcx.` in preparation for implementing 16-byte lock free atomic operations on AIX. Add a new register class `g8prc` for these instructions, since these instructions require even-odd register pair. Reviewed By: nemanjai, jsji, #powerpc Differential Revision: https://reviews.llvm.org/D103010
2021-06-11[PowerPC] Relax register superclasses for paired memopsQiu Chaofan1-7/+21
Relaxing superclass constraint for VSX register classes helps reducing 32-byte spills and copies when register pressure is high. In test case affected, some of them introduces more copies due to new allocation order. However, this patch should not be the root cause, and we may be able to fix it in other places of register allocation. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D104006
2021-05-13[PowerPC] Add ROP Protection to prologue and epilogueStefan Pintilie1-0/+10
Added hashst to the prologue and hashchk to the epilogue. The hash for the prologue and epilogue must always be stored as the first element in the local variable space on the stack. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D99377
2021-05-10[PowerPC] Spilling to registers does not require frame index scavengingStefan Pintilie1-4/+24
If spills are to registers instead of to the stack then a copy will be used and frame index scavenging is not required. This patch adds debug info to frame index scavenging and makes sure that spilling to registers does not cause frame index scavenging. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D101360
2021-05-03[AIX] Remove unused vector registers from allocation order in the default ↵Zarko Todorovski1-4/+19
AltiVec ABI The previous implementation of the default AltiVec ABI marked registers V20-V31 as reserved. This failed to prevent reserved VFRC registers being allocated. In this patch instead of marking the registers reserved we remove unallowed registers from the allocation order completely. This is a slight rework of an implementation by @nemanjai Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D100050
2021-03-31[PowerPC] [MLICM] Enable hoisting of caller preserved registers on AIXShimin Cui1-9/+7
On ppc64 linux , MachineLICM will hoist caller preserved registers, including TOC loads of the global variable address, out of loops. This is to enable this on AIX for both ppc64 and ppc32. Differential Revision: https://reviews.llvm.org/D99076
2021-03-30[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functionsTomas Matheson1-1/+1
Currently needsStackRealignment returns false if canRealignStack returns false. This means that the behavior of needsStackRealignment does not correspond to it's name and description; a function might need stack realignment, but if it is not possible then this function returns false. Furthermore, needsStackRealignment is not virtual and therefore some backends have made use of canRealignStack to indicate whether a function needs stack realignment. This patch attempts to clarify the situation by separating them and introducing new names: - shouldRealignStack - true if there is any reason the stack should be realigned - canRealignStack - true if we are still able to realign the stack (e.g. we can still reserve/have reserved a frame pointer) - hasStackRealignment = shouldRealignStack && canRealignStack (not target customisable) Targets can now override shouldRealignStack to indicate that stack realignment is required. This change will make it easier in a future change to handle the case where we need to realign the stack but can't do so (for example when the register allocator creates an aligned spill after the frame pointer has been eliminated). Differential Revision: https://reviews.llvm.org/D98716 Change-Id: Ib9a4d21728bf9d08a545b4365418d3ffe1af4d87
2021-03-05[PowerPC][AIX] Enable the default AltiVec ABI on AIXZarko Todorovski1-14/+40
This patch adds support for the default AltiVec ABI for AIX. Vector registers 20 through 31 are marked as reserved and cannot be used in the default ABI. This patch adds handling for this case and also remove the default AltiVec ABI errors. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D96351
2021-03-03[PowerPC] Allow spilling GPR to VSR on AIXQiu Chaofan1-1/+1
This patch enables spilling GPR to VSRs instead of stack under AIX ABI. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D97367
generated by cgit v1.1 at 2025-08-03 22:49:21 +0000