| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 4 days | [ARM] Remove unnecessary casts (NFC) (#148533) | Kazu Hirata | 1 | -20/+19 |
| 2025-06-17 | [llvm] annotate interfaces in llvm/Target for DLL export (#143615) | Andrew Rogers | 1 | -1/+2 |
| 2025-03-19 | [ARM] Use MCPhysReg instead of uint16_t for arrays of registers. NFC | Craig Topper | 1 | -7/+7 |
| 2024-11-07 | [ARM] Allow spilling FPSCR for MVE adc/sbc intrinsics (#115174) | Oliver Stannard | 1 | -0/+7 |
| 2024-10-18 | [ARM] Use ARM::NoRegister in more places. NFC | David Green | 1 | -4/+4 |
| 2024-10-17 | Fix MSVC signed/unsigned mismatch warning. NFC. | Simon Pilgrim | 1 | -1/+1 |
| 2024-10-17 | [ARM] Fix problems with register list in vscclrm (#111825) | John Brawn | 1 | -18/+34 |
| 2024-10-16 | [ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp (#112507) | Karl-Johan Karlsson | 1 | -2/+3 |
| 2024-09-21 | [ARM] Use MCRegister in more places. NFC | Craig Topper | 1 | -1/+1 |
| 2024-03-11 | [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm | Sivan Shani | 1 | -0/+23 |
| 2024-02-29 | Revert "[llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)" | Tomas Matheson | 1 | -23/+0 |
| 2024-02-28 | [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116) | SivanShani-Arm | 1 | -0/+23 |
| 2023-10-10 | Use llvm::endianness::{big,little,native} (NFC) | Kazu Hirata | 1 | -3/+3 |
| 2023-10-09 | Use llvm::endianness{,::little,::native} (NFC) | Kazu Hirata | 1 | -1/+1 |
| 2023-09-01 | [llvm] Fix duplicate word typos. NFC | Fangrui Song | 1 | -1/+1 |
| 2023-06-26 | Move SubtargetFeature.h from MC to TargetParser | Job Noorman | 1 | -1/+1 |
| 2023-02-17 | Simplify with hasFeature. NFC | Fangrui Song | 1 | -5/+5 |
| 2023-02-13 | [ARM] Use llvm::rotl and llvm::rotr (NFC) | Kazu Hirata | 1 | -1/+1 |
| 2023-01-28 | [Target] Use llvm::count{l,r}_{zero,one} (NFC) | Kazu Hirata | 1 | -2/+2 |
| 2023-01-23 | [MC] Make more use of MCInstrDesc::operands. NFC. | Jay Foad | 1 | -8/+8 |
| 2023-01-12 | [ARM] Use MCInstrInfo::get in ARMDisassembler instead of reinventing it | Jay Foad | 1 | -37/+40 |
| 2022-12-07 | [TableGen] More named sub-operands work. | James Y Knight | 1 | -0/+14 |
| 2022-10-28 | [llvm-tblgen] NFC: Simplify DecoderEmitter. | James Y Knight | 1 | -15/+0 |
| 2022-08-08 | [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC | Fangrui Song | 1 | -4/+4 |
| 2022-08-08 | [llvm-objdump,ARM] Fix big-endian AArch32 disassembly. | Simon Tatham | 1 | -6/+14 |
| 2022-07-26 | [MC,llvm-objdump,ARM] Target-dependent disassembly resync policy. | Simon Tatham | 1 | -0/+30 |
| 2022-05-25 | [MCDisassembler] Disambiguate Size parameter in tryAddingSymbolicOperand() | Maksim Panchenko | 1 | -1/+2 |
| 2022-05-15 | Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h` | Sheng | 1 | -1/+1 |
| 2022-03-25 | [Disassember][NFCI] Use strong type for instruction decoder | Maksim Panchenko | 1 | -526/+747 |
| 2022-03-17 | [ARM] Fix Decode of tsb csync | Archibald Elliott | 1 | -0/+15 |
| 2021-11-30 | [clang][ARM] PACBTI-M assembly support | Ties Stuij | 1 | -2/+65 |
| 2021-10-08 | Move TargetRegistry.(h|cpp) from Support to MC | Reid Kleckner | 1 | -1/+1 |
| 2021-09-02 | [ARM] Add a tail-predication loop predicate register | David Green | 1 | -3/+6 |
| 2021-08-16 | [ARM] Create MQQPR and MQQQQPR register classes | David Green | 1 | -10/+12 |
| 2021-04-25 | [ARM][disassembler] Fix incorrect number of MCOperands generated by the disas... | Min-Yih Hsu | 1 | -7/+8 |
| 2020-11-18 | ADT: Add assertions to SmallVector::insert, etc., for reference invalidation | Duncan P. N. Exon Smith | 1 | -1/+2 |
| 2020-07-22 | [ARM] Fix Asm/Disasm of TBB/TBH instructions | David Spickett | 1 | -1/+3 |
| 2020-04-07 | [ARM] Remove condition that could never be true | Peter Smith | 1 | -1/+3 |
| 2020-02-17 | [ARM] Add initial support for Custom Datapath Extension (CDE) | Mikhail Maltsev | 1 | -1/+40 |
| 2020-01-23 | [ARM,MVE] Revise immediate VBIC/VORR to look more like NEON. | Simon Tatham | 1 | -14/+0 |
| 2020-01-14 | CMake: Make most target symbols hidden by default | Tom Stellard | 1 | -1/+1 |
| 2020-01-14 | [ARM][Thumb2] Fix ADD/SUB invalid writes to SP | Diogo Sampaio | 1 | -4/+69 |
| 2020-01-11 | [Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction() | Fangrui Song | 1 | -13/+7 |
| 2020-01-10 | Reverting, broke some bots. Need further investigation. | Diogo Sampaio | 1 | -69/+4 |
| 2020-01-10 | [ARM][Thumb2] Fix ADD/SUB invalid writes to SP | Diogo Sampaio | 1 | -4/+69 |
| 2019-09-09 | [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings | Oliver Stannard | 1 | -0/+6 |
| 2019-07-28 | [ARM] MVE VPNOT | David Green | 1 | -0/+10 |
| 2019-07-23 | [ARM] Rename NEONModImm to VMOVModImm. NFC | David Green | 1 | -4/+4 |
| 2019-07-19 | [ARM] Add <saturate> operand to SQRSHRL and UQRSHLL | Mikhail Maltsev | 1 | -0/+7 |
| 2019-06-28 | [ARM] Fix integer UB in MVE load/store immediate handling. | Simon Tatham | 1 | -2/+2 |
