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path: root/llvm/lib/Target/ARM/ARMInstrInfo.td
AgeCommit message (Expand)AuthorFilesLines
2025-07-15Remove Native Client support (#133661)Brad Smith1-18/+2
2025-07-15[WebAssembly] Add patterns for relaxed madd (#147487)jjasmine1-5/+0
2025-05-01[DAG] Use SDValue for PatFrag checks (#137519)David Green1-5/+5
2025-04-28[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/6...Craig Topper1-4/+4
2025-04-25[SelectionDAG][Targets] Replace atomic_load_8/atomic_load_16 with atomic_load...Craig Topper1-8/+8
2025-04-01[ARM] Use tablegen HasOneUse. NFCDavid Green1-9/+6
2025-01-13[ARM] Add mayStore to more store instructionsDavid Green1-3/+8
2025-01-07[ARM] Record store with pre/post-indexed addressing as `mayStore`Antonio Frighetto1-1/+2
2024-12-16[ARM][Thumb2] Allow 2-operand variants of `[us]div` (#119976)Dmitry Chestnykh1-0/+2
2024-12-12[TableGen] Replace WantRoot/WantParent SDNode properties with flags (#119599)Sergei Barannikov1-19/+18
2024-12-07Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)Sergei Barannikov1-64/+84
2024-12-02Revert "[ARM] Stop gluing ALU nodes to branches / selects" (#118232)Martin Storsjö1-84/+64
2024-11-30[ARM] Stop gluing ALU nodes to branches / selects (#116970)Sergei Barannikov1-64/+84
2024-11-19[ARM] Stop gluing 1-bit shifts (#116547)Sergei Barannikov1-15/+27
2024-11-18[ARM] Use getSignedTargetConstant. NFCCraig Topper1-4/+4
2024-10-23[llvm][ARM] Correct the properties of trap instructions (#113287)David Spickett1-2/+2
2024-09-05[CodeGen] Add generic INIT_UNDEF pseudo (#106744)Nikita Popov1-12/+0
2024-09-02[ARM] Fix failure to register-allocate CMP_SWAP_64 pseudo-inst (#106721)Oliver Stannard1-2/+15
2024-08-17[ARM] Use SelectonDAG::getSignedConstant.Craig Topper1-2/+4
2024-06-15[ARM] Remove duplicate custom SDag node (NFCI) (#93419)Sergei Barannikov1-9/+0
2024-04-30Do not use R12 for indirect tail calls with PACBTI (#82661)Eleanor Bonnici1-1/+10
2024-02-26[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add suppor...Jack Styles1-0/+12
2024-02-07[GlobalISel][ARM] Support missing case for G_CONSTANT (#80555)Serge Pavlov1-2/+4
2023-09-08[ARM] Change CRC predicate to just HasCRCDavid Green1-1/+1
2023-08-31SelectionDAG: Swap operands of atomic_storeMatt Arsenault1-6/+6
2023-06-22[ARM] add Thumb-1 8-bit movs/adds relocations to LLVMTies Stuij1-2/+17
2023-06-15[ARM,AArch64] Add a full set of -mtp= options.Simon Tatham1-1/+5
2023-04-05[ARM] Fold fadd of vcmul into vcmlaDavid Green1-0/+5
2023-04-02[Targets] Rename Flag->Glue. NFCCraig Topper1-13/+13
2023-01-20[ARM][AArch64] Switch to generic MEMBARRIER nodePhilip Reames1-7/+1
2023-01-09[ARM] Fold And/Or into CSel if possibleDavid Green1-0/+6
2022-12-08[Arm][AArch64] Add support for v8.9-A/v9.4-A base extensionsLucas Prates1-0/+4
2022-10-01[ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstrFilipp Zhinkin1-0/+7
2022-06-02[ARM] Add SEH opcodes in frame loweringMartin Storsjö1-0/+21
2022-03-22[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vnc...Craig Topper1-1/+1
2022-03-17[ARM] Fix Decode of tsb csyncArchibald Elliott1-0/+1
2022-02-07[ARM] Undeprecate complex IT blocksMark Murray1-2/+1
2022-02-01[ARM] Make getInstSizeInBytes() use instruction size from InstrInfo.tdtyb08071-4/+15
2021-11-25[DAG] SimplifyDemandedBits - simplify rotl/rotr to shl/srl (REAPPLIED)Simon Pilgrim1-0/+8
2021-11-24Revert "[DAG] SimplifyDemandedBits - simplify rotl/rotr to shl/srl"Benjamin Kramer1-8/+0
2021-11-24[DAG] SimplifyDemandedBits - simplify rotl/rotr to shl/srlSimon Pilgrim1-0/+8
2021-09-10[ARM] Remove unused tblgen arguments. NFCDavid Green1-5/+4
2021-08-05[ARM][llvm-objdump] Annotate PC-relative memory operands of VLDR instructionsIgor Kudrin1-1/+1
2021-08-05[ARM][llvm-objdump] Annotate PC-relative memory operandsIgor Kudrin1-6/+10
2021-07-11[ARM] Add lowering of uadd_sat to uq{add|sub}8 and uq{add|sub}16Daniel Egger1-0/+16
2021-06-21Rename MachineMemOperand::getOrdering -> getSuccessOrdering.Eli Friedman1-2/+2
2021-05-28ARM: support mandatory tail calls for tailcc & swifttailccTim Northover1-6/+9
2021-05-03Revert "[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0"Tomas Matheson1-31/+0
2021-05-03[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0Tomas Matheson1-0/+31
2021-04-30Revert "[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0"Tomas Matheson1-31/+0
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