aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/ARM/ARMISelLowering.h
AgeCommit message (Expand)AuthorFilesLines
13 days[IA] Support vp.store in lowerinterleavedStore (#149605)Philip Reames1-1/+2
2025-07-17[IA] Support vp.load in lowerInterleavedLoad [nfc-ish] (#149174)Philip Reames1-1/+1
2025-07-10[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to t...Boyao Wang1-1/+1
2025-06-29[ARM] Override hasAndNotCompare (#145441)AZero131-0/+5
2025-06-19ARM: Move ABI helpers from Subtarget to TargetMachine (#144680)Matt Arsenault1-0/+3
2025-06-19ARM: Move declaration of supportSplitCSR to be public (#144679)Matt Arsenault1-5/+5
2025-05-29[SDAG] Make Select-with-Identity-Fold More Flexible; NFC (#136554)Marius Kamp1-2/+3
2025-01-20[Mips] Fix compiler crash when returning fp128 after calling a functi… (#11...yingopq1-1/+1
2024-12-21[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119...Sergei Barannikov1-2/+4
2024-12-19[ARM] Fix BF16 lowering with FullFP16David Green1-0/+1
2024-12-07Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)Sergei Barannikov1-3/+1
2024-12-02Revert "[ARM] Stop gluing ALU nodes to branches / selects" (#118232)Martin Storsjö1-1/+3
2024-11-30[ARM] Stop gluing ALU nodes to branches / selects (#116970)Sergei Barannikov1-3/+1
2024-11-19[ARM] Stop gluing 1-bit shifts (#116547)Sergei Barannikov1-4/+4
2024-10-25[ARM] Optimise byval arguments in tail-callsOliver Stannard1-0/+16
2024-10-17[PowerPC][ISelLowering] Support -mstack-protector-guard=tls (#110928)Keith Packard1-1/+1
2024-10-09[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)Jeffrey Byrnes1-2/+0
2024-06-20[ARM] CMSE security mitigation on function arguments and returned values (#89...Lucas Duarte Prates1-1/+1
2024-06-15[ARM] Remove duplicate custom SDag node (NFCI) (#93419)Sergei Barannikov1-2/+1
2024-05-03[ARM/X86] Standardize the isEligibleForTailCallOptimization prototypes (#90688)Reid Kleckner1-6/+2
2024-04-15[ARM] Don't include IRBuilder.h in ARMISelLowering.h (NFC)Nikita Popov1-1/+1
2024-02-02[ARM] Switch to soft promoting half types. (#80440)Harald van Dijk1-0/+4
2024-01-25[llvm] Move CodeGenTypes library to its own directory (#79444)Nico Weber1-1/+1
2023-12-18[ARM][FPEnv] Lowering of fpmode intrinsics (#74054)Serge Pavlov1-0/+10
2023-09-25[TargetLowering] Deduplicate choosing InlineAsm constraint between ISels (#67...Nick Desaulniers1-1/+1
2023-09-13reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66264)Nick Desaulniers1-10/+10
2023-09-13Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)"Reid Kleckner1-10/+10
2023-09-13[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)Nick Desaulniers1-10/+10
2023-07-13Revert "[CodeGen] Store SP adjustment in MachineBasicBlock. NFCI."Oliver Stannard1-2/+0
2023-07-12[CodeGen] Store SP adjustment in MachineBasicBlock. NFCI.Jay Foad1-0/+2
2023-05-30[CodeGen] Refactor IR generation functions to use IRBuilder in ComplexDeinter...Igor Kirillov1-1/+1
2023-05-16[ARM] Remove unused declaration RemapAddSubWithFlagsKazu Hirata1-5/+0
2023-05-06[ARM] Remove unused declaration LowerGLOBAL_OFFSET_TABLEKazu Hirata1-1/+0
2023-05-03Restore CodeGen/MachineValueType.h from `Support`NAKAMURA Takumi1-1/+1
2023-04-28[ARM] Enable shouldFoldSelectWithIdentityConstant for MVEDavid Green1-0/+3
2023-04-02[Targets] Rename Flag->Glue. NFCCraig Topper1-6/+6
2023-02-14Revert "[CGP] Add generic TargetLowering::shouldAlignPointerArgs() implementa...Jake Egan1-3/+2
2023-02-09[CGP] Add generic TargetLowering::shouldAlignPointerArgs() implementationAlex Richardson1-2/+3
2023-02-08[DAG] Fold Op(vecreduce(a), vecreduce(b)) into vecreduce(Op(a,b))David Green1-0/+4
2023-02-07[ARM] Add various tests for reductions of shuffles. NFCDavid Green1-2/+1
2023-01-14[Codegen][LegalizeIntegerTypes] New legalization strategy for scalar shifts: ...Roman Lebedev1-1/+3
2022-12-19[Intrinsic] Rename flt.rounds intrinsic to get.roundingQiu Chaofan1-1/+1
2022-12-01TargetLowering: convert Optional to std::optionalKrzysztof Parzyszek1-9/+9
2022-11-17[AMDGPU] Allow finer grain control of an unaligned access speedStanislav Mekhanoshin1-1/+1
2022-11-14[ARM][CodeGen] Add support for complex deinterleavingNicholas Guy1-0/+9
2022-09-26[ARM] Enable and/cmp0 foldingMomchil Velikov1-0/+2
2022-08-24[X86] Promote i8/i16 CTTZ (BSF) instructions and remove speculation branchSimon Pilgrim1-2/+2
2022-08-18[NFCI] Move cost estimation from TargetLowering to TargetTransformInfo.Daniil Fukalov1-8/+0
2022-07-19[DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >> Sh...Simon Pilgrim1-0/+2
2022-06-14[NFC][Alignment] Use Align in shouldAlignPointerArgsGuillaume Chatelet1-1/+1