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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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2025-05-29[ARM] Remove unused enable-arm-3-addr-conv (#141850)David Green1-3/+0
2025-04-17[ARM] Use helper class for emitting CFI instructions into MIR (#135994)Sergei Barannikov1-10/+0
2025-02-24[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister....Craig Topper1-1/+1
2025-01-22[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (N...Venkata Ramanaiah Nalamothu1-12/+11
2025-01-20[ARM] Use MCRegister instead of unsigned. NFCCraig Topper1-2/+2
2024-11-13[LLVM][ARM] Latency mutations for cortex m55,m7 and m85 (#115153)Nashe Mncube1-0/+28
2024-09-05[CodeGen] Add generic INIT_UNDEF pseudo (#106744)Nikita Popov1-13/+0
2024-08-27[MachineOutliner][NFC] Refactor (#105398)Kyungwoo Lee1-2/+4
2024-08-27[TII][RISCV] Add renamable bit to copyPhysReg (#91179)Piyou Chen1-1/+2
2024-07-24MachineOutliner: Use PM to query MachineModuleInfo (#99688)Matt Arsenault1-2/+4
2024-04-30Do not use R12 for indirect tail calls with PACBTI (#82661)Eleanor Bonnici1-0/+1
2024-02-26[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add suppor...Jack Styles1-0/+18
2024-02-01[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)Philip Reames1-4/+4
2024-01-26[NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate...Shengchen Kan1-2/+2
2023-12-01TargetInstrInfo: make getOperandLatency return optional (NFC) (#73769)Ramkumar Ramachandra1-37/+39
2023-03-20[NFC][Outliner] Delete default ctors for Candidate & OutlinedFunction.Amara Emerson1-1/+1
2023-02-09[MachineOutliner] Make getOutliningType partially target-independentduk1-1/+1
2022-12-17[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStac...Christudasan Devadasan1-7/+8
2022-12-04[Target] llvm::Optional => std::optionalFangrui Song1-5/+5
2022-07-18CodeGen: Remove AliasAnalysis from regallocMatt Arsenault1-2/+1
2022-06-02[ARM] Add SEH opcodes in frame loweringMartin Storsjö1-0/+20
2022-04-29Reapply [CodeGen][ARM] Enable Swing Module Scheduling for ARMDavid Penry1-0/+5
2022-04-28Revert "[CodeGen][ARM] Enable Swing Module Scheduling for ARM"David Penry1-5/+0
2022-04-28[CodeGen][ARM] Enable Swing Module Scheduling for ARMDavid Penry1-0/+5
2022-02-16[MachineOutliner] NFC: Hide LRU-related stuff behind helper functionsJessica Paquette1-2/+2
2021-12-07[ARM] Implement PAC return address signing mechanism for PACBTI-MTies Stuij1-16/+11
2021-12-02[ARM] Introduce i8neg and i8pos addressing modesDavid Green1-0/+4
2021-12-02[ARM] Correct range in isLegalAddressImmDavid Green1-9/+9
2021-12-01[ARM] Implement BTI placement pass for PACBTI-MTies Stuij1-0/+2
2021-11-17[CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddressJay Foad1-2/+2
2021-09-23[TII] Remove the MFI argument to convertToThreeAddress. NFC.Jay Foad1-2/+1
2021-08-30[InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI)Nikita Popov1-3/+3
2021-06-13[ARM] Introduce t2WhileLoopStartTPDavid Green1-7/+2
2021-04-16[ARM] Prevent phi-node-elimination from generating copy above t2WhileLoopStartLRMalhar Jajoo1-1/+2
2021-03-11[ARM] Improve WLS loweringDavid Green1-1/+2
2021-02-24[ARM] Expand the range of allowed post-incs in load/store optimizerDavid Green1-0/+4
2021-02-19Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer"David Green1-3/+0
2021-02-18[ARM] Expand the range of allowed post-incs in load/store optimizerDavid Green1-0/+3
2021-01-19[ARM][MachineOutliner] Add stack fixup featureYvan Roux1-0/+10
2021-01-16[ARM] Add low overhead loops terminators to AnalyzeBranchDavid Green1-0/+5
2020-12-23[ARM] Add bank conflict hazardingDavid Penry1-0/+4
2020-12-19[ARM] harden-sls-blr: avoid r12 and lr in indirect calls.Kristof Beyls1-0/+7
2020-12-19[ARM] Harden indirect calls against SLSKristof Beyls1-0/+45
2020-12-19[ARM] Implement harden-sls-retbr for Thumb modeKristof Beyls1-1/+3
2020-12-19[ARM] Implement harden-sls-retbr for ARM modeKristof Beyls1-0/+11
2020-12-11[ARM] Make t2DoLoopStartTP a terminatorDavid Green1-1/+2
2020-12-10[ARM][RegAlloc] Add t2LoopEndDecDavid Green1-0/+4
2020-12-07[ARM] Revert low overhead loops with calls before registry allocation.David Green1-50/+0
2020-11-10[ARM] Introduce t2DoLoopStartTPDavid Green1-0/+1
2020-11-09[ARM][MachineOutliner] Emit more CFI instructionsMomchil Velikov1-2/+23
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