aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AMDGPU/VOP1Instructions.td
AgeCommit message (Expand)AuthorFilesLines
22 hours[AMDGPU] Remove dead code in VOP1 tablegen (NFC) (#151932)Chris Jackson1-12/+0
2025-07-18[AMDGPU] Add support for `v_sat_pk4_i4_[i8,u8]` on gfx1250 (#149528)Shilei Tian1-0/+5
2025-07-18[AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250 (#149518)Shilei Tian1-0/+8
2025-07-18[AMDGPU] Add support for `v_prng_b32` on gfx1250 (#149450)Shilei Tian1-0/+1
2025-07-18[AMDGPU] Add support for `v_tanh_f16` on gfx1250 (#149439)Shilei Tian1-0/+5
2025-07-17[AMDGPU] Add support for `v_tanh_f32` on gfx1250 (#149360)Shilei Tian1-0/+4
2025-07-17[AMDGPU] Add support for `v_cos_bf16` on gfx1250 (#149355)Shilei Tian1-0/+2
2025-07-17[AMDGPU] Add support for `v_sin_bf16` on gfx1250 (#149241)Shilei Tian1-0/+2
2025-07-17[AMDGPU] Add support for `v_exp_bf16` on gfx1250 (#149229)Shilei Tian1-0/+2
2025-07-16[AMDGPU] Add support for `v_log_bf16` on gfx1250 (#149201)Shilei Tian1-0/+2
2025-07-16[AMDGPU] Add support for `v_rsq_bf16` on gfx1250 (#149194)Shilei Tian1-0/+2
2025-07-15[AMDGPU] Add support for `v_sqrt_bf16` on gfx1250 (#148921)Shilei Tian1-0/+2
2025-07-15[AMDGPU] Add support for `v_rcp_bf16` on gfx1250 (#148916)Shilei Tian1-0/+2
2025-07-14[AMDGPU] Add support for `v_tanh_bf16` on gfx1250 (#147425)Shilei Tian1-0/+5
2025-07-10[AMDGPU] Disable DPP with v_mov_b64 on gfx1250 (#148054)Stanislav Mekhanoshin1-2/+6
2025-07-09[AMDGPU] gfx1250 MC support for v_mov_b64 (#147859)Stanislav Mekhanoshin1-5/+11
2025-07-09[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)Brox Chen1-3/+20
2025-07-08[AMDGPU] Add support for `v_cvt_f32_fp8` on gfx1250 (#147579)Shilei Tian1-7/+25
2025-07-02[AMDGPU][MC] Fix disassembly for v_permlane16_swap_b32 for GFX950 (#146600)Jun Wang1-2/+2
2025-06-30[AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (#146305)Shilei Tian1-0/+5
2025-06-30[AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250 (#146302)Shilei Tian1-2/+19
2025-06-25[AMDGPU] Add support for `v_cvt_pk_f16_bf8` on gfx1250 (#145753)Shilei Tian1-0/+4
2025-06-25[AMDGPU] Add support for `v_cvt_pk_f16_fp8` on gfx1250 (#145747)Shilei Tian1-0/+16
2025-06-25[AMDGPU] Add the support for `v_cvt_f32_bf16` on gfx1250 (#145632)Shilei Tian1-2/+23
2025-06-20[AMDGPU] Fix to prevent sinking of PERMLANE_SWAP instruction (#144423)Vigneshwar Jayakumar1-1/+5
2025-06-17[AMDGPU] Remove AsmVOP3OpSel field completely. NFCI. (#144574)Stanislav Mekhanoshin1-1/+0
2025-05-16[AMDGPU] Automate creation of byte_sel dags. NFCI. (#140155)Stanislav Mekhanoshin1-11/+0
2025-05-15[AMDGPU] Cleanup bytesel variables. NFC. (#140131)Stanislav Mekhanoshin1-1/+1
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-2/+0
2025-05-05[AMDGPU][True16][CodeGen] readfirstlane for vgpr16 copy to sgpr32 (#118037)Brox Chen1-8/+1
2025-04-02[AMDGPU][True16][CodeGen] Implement sgpr folding in true16 (#128929)Brox Chen1-0/+1
2025-04-02[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4 (#133741)Juan Manuel Martinez CaamaƱo1-1/+1
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve1-1/+1
2025-01-29[AMDGPU][NFC] Simplify t16/fake16 TableGen definitions. (#122693)Ivan Kosarev1-25/+25
2025-01-06[AMDGPU][True16][MC] true16 for v_cvt_u32_u16 (#120646)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_rndne_f16 (#120691)Brox Chen1-1/+1
2025-01-03 [AMDGPU][True16][MC] true16 for v_cos_f16 (#120639)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_cvt_i32_i16 (#120645)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_fract_f16 (#120647)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_frexp_mant_f16 (#120653)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_sin_f16 (#120692)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_not_b16 (#120659)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_trunc_f16 (#120693)Brox Chen1-1/+1
2025-01-03[AMDGPU][True16][MC] true16 for v_sat_pk_u8_i16 (#120634)Brox Chen1-1/+1
2024-11-22AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx950 (#117260)Matt Arsenault1-0/+46
2024-11-18AMDGPU: Add V_CVT_F32_BF16 for gfx950 (#116311)Matt Arsenault1-0/+5
2024-11-18AMDGPU: Add v_prng_b32 instruction for gfx950 (#116310)Matt Arsenault1-0/+5
2024-11-18AMDGPU: Copy correct predicates for SDWA reals (#116288)Matt Arsenault1-2/+2
2024-11-14[AMDGPU][True16][MC] Implement V_CVT_PK_F32_FP8/BF8 (#116106)Joe Nash1-22/+29
2024-11-14[AMDGPU][True16][MC] Copy True16Predicate from pseudo to real in VOP1 (#116098)Joe Nash1-1/+2