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16 hours[AMDGPU]: Unpack packed instructions overlapped by MFMAs post-RA scheduling (...Akash Dutta3-5/+398
21 hoursCodeGen: Add RegisterClass by HwMode (#158269)Matt Arsenault3-4/+9
23 hours[SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD transforms (#146074)Fabian Ritter2-49/+13
24 hours[AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (#145330)Fabian Ritter2-6/+7
32 hoursAMDGPU: Remove unnecessary AGPR legalize logic (#159491)Matt Arsenault1-13/+0
33 hours[AMDGPU] gfx1251 VOP3 dpp support (#159654)Stanislav Mekhanoshin3-51/+92
34 hours[AMDGPU] gfx1251 VOP2 dpp support (#159641)Stanislav Mekhanoshin1-34/+45
36 hours[AMDGPU] gfx1251 VOP1 dpp support (#159637)Stanislav Mekhanoshin1-22/+43
43 hours[AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (#143881)Fabian Ritter1-5/+20
44 hours[AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (#1...Petar Avramovic1-6/+75
2 daysAMDGPU: Remove unnecessary operand legalization for WMMAs (#159370)Matt Arsenault1-15/+0
2 daysAMDGPU: Constrain regclass when replacing SGPRs with VGPRs (#159369)Matt Arsenault1-1/+4
2 daysAMDGPU: Set RegTupleAlignUnits on _Lo256_Align2 class (#159383)Matt Arsenault1-1/+3
2 days[AMDGPU] Mark cluster_workgroup_id_* intrinsics always uniform (#159439)Stanislav Mekhanoshin1-0/+8
3 days[AMDGPU] Add gfx1251 subtarget (#159430)Stanislav Mekhanoshin3-0/+10
3 days[AMDGPU] Fold copies of constant physical registers into their uses (#154410)Stanislav Mekhanoshin1-4/+11
3 days[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 I...Brox Chen4-1/+30
3 daysAMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs (#159283)Matt Arsenault1-4/+10
3 daysAMDGPU: Remove subtarget feature hacking in AsmParser (#159227)Matt Arsenault2-14/+3
3 days[TableGen] Add mapping from processor ID to resource index for packetizer (#1...Luo, Yuanke1-0/+5
3 days[AMDGPU] Prevent re-visits in LowerBufferFatPointers (#159168)Krzysztof Drewniak1-0/+6
3 days[AMDGPU] Add s_cluster_barrier on gfx1250 (#159175)Stanislav Mekhanoshin3-9/+69
4 days[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)Shilei Tian3-25/+32
4 days[AMDGPU] Change `scale_sel` to be 4 bits (#157900)Shilei Tian2-4/+3
4 days[AMDGPU] Add aperture classes to VS_64 (#158823)Stanislav Mekhanoshin1-3/+5
4 days[AMDGPU] Elide bitcast fold i64 imm to build_vector (#154115)Janek van Oirschot3-1/+55
4 daysAMDGPU: Try to unspill VGPRs after rewriting MFMAs to AGPR form (#154323)Matt Arsenault1-4/+171
4 days[AMDGPU] Use larger immediate values in S_NOP (#158990)Jay Foad2-1/+12
4 days[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#15...Stanislav Mekhanoshin2-23/+5
4 days[AMDGPU] Drop high 32 bits of aperture registers (#158725)Stanislav Mekhanoshin2-17/+25
4 days[AMDGPU][MC] Keep MCOperands unencoded. (#158685)Ivan Kosarev4-71/+46
4 daysCodeGen: Surface shouldRewriteCopySrc utility function (#158524)Matt Arsenault1-15/+2
4 days[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)Carl Ritson11-386/+338
5 days[AMDGPU] Add the support for `.cluster_dims` code object metadata (#158721)Shilei Tian2-8/+28
5 days[AMDGPU][Attributor] Add `AAAMDGPUClusterDims` (#158076)Shilei Tian3-2/+167
5 days[AMDGPU][AsmParser] Simplify getting source locations of operands. (#158323)Ivan Kosarev1-186/+102
5 days[AMDGPU][NFC] Refactor FLAT_Global_* pseudos. (#120244)sstipano1-87/+68
5 daysAMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)macurtis-amd1-1/+7
7 daysAMDGPU: Relax verifier for agpr/vgpr loads and stores (#158391)Matt Arsenault1-1/+1
7 days[AMDGPU] Support lowering of cluster related instrinsics (#157978)Shilei Tian12-30/+567
8 days[AMDGPU] Remove scope check in SIInsertWaitcnts::generateWaitcntInstBefore (#...choikwa1-7/+1
8 daysCodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault4-17/+14
8 daysAMDGPU: Move spill pseudo special case out of adjustAllocatableRegClass (#158...Matt Arsenault2-7/+7
8 days[NFC][AMDGPU][SIMemoryLegalizer] remove effectively empty function (#156806)Sameer Sahasrabuddhe1-39/+0
8 daysCodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)Matt Arsenault2-4/+4
8 daysAMDGPU: Remove MIMG special case in adjustAllocatableRegClass (#158184)Matt Arsenault1-2/+1
8 days[AMDGPUPromoteAlloca][NFC] Avoid unnecessary APInt/int64_t conversions (#157864)Fabian Ritter1-12/+10
8 days[AMDGPU] Remove an unused variable (NFC)Jie Fu1-1/+0
8 daysAMDGPU: Fix returning wrong type for stack passed sub-dword arguments (#158002)Matt Arsenault2-27/+42
8 daysAMDGPU: Relax legal register operand constraint (#157989)Matt Arsenault1-5/+3
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