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path: root/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
5 daysAMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (#14...Changpeng Fang1-0/+6
7 days[AMDGPU] Add gfx1250 v_fmac_f64 implementation (#148725)Stanislav Mekhanoshin1-0/+1
11 days[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)Stanislav Mekhanoshin1-24/+129
12 days[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin1-1/+1
2025-07-03AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)Changpeng Fang1-0/+24
2025-06-25[AMDGPU][GFX1250] Insert S_WAIT_XCNT for SMEM and VMEM load-stores (#145566)Christudasan Devadasan1-0/+9
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus1-16/+46
2025-06-21[AMDGPU] Rename call instructions from b64 to i64 (#145103)Stanislav Mekhanoshin1-0/+4
2025-06-05[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)Diana Picus1-65/+0
2025-05-14[AMDGPU] Use std::optional::value_or (NFC) (#140006)Kazu Hirata1-1/+1
2025-05-13Reapply "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during sched...Lucas Ramirez1-0/+2
2025-05-09Revert "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during schedu...Vitaly Buka1-2/+0
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-2/+0
2025-05-08[AMDGPU][NFC] Remove unused operand types. (#139062)Ivan Kosarev1-6/+0
2025-05-08[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (#1...Lucas Ramirez1-0/+2
2025-04-13[AMDGPU][True16][MC] fix fmac_f16_t16 vop3 format (#135464)Brox Chen1-0/+2
2025-03-29[NFC][AMDGPU] clang-format `AMDGPUBaseInfo.[h,cpp]` (#133559)Shilei Tian1-135/+137
2025-03-27[AMDGPU] Add a new function `getIntegerPairAttribute` (#133271)Shilei Tian1-8/+17
2025-03-21Reapply "[AMDGPU] Use COV6 by default (#118515)" (#130963)Shilei Tian1-1/+1
2025-03-19[AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (#130047)Diana Picus1-0/+6
2025-03-17[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)Alex Voicu1-1/+1
2025-03-14[NFC][AMDGPU] Replace more direct arch comparison with isAMDGCN() (#131379)Shilei Tian1-1/+1
2025-03-12[AMDGPU] Merge consecutive wait_alu instruction (#128916)Ana Mihajlovic1-0/+36
2025-03-03[AMDGPU] Simplify conditional expressions. NFC. (#129228)Jay Foad1-15/+15
2025-02-25[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)Brox Chen1-0/+2
2025-02-18[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#1...Brox Chen1-0/+1
2025-02-18Revert "[AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (#11...Nikita Popov1-1/+0
2025-02-18[AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (#114500)Brox Chen1-0/+1
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson1-0/+36
2025-01-22[AMDGPU] Fix unreachable reg bit width (#122107)Shoreshen1-0/+2
2024-12-11[AMDGPU][Attributor] Make `AAAMDFlatWorkGroupSize` honor existing attribute (...Shilei Tian1-5/+16
2024-12-11[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)Pravin Jagtap1-6/+14
2024-12-05[AMDGPU][NFC] Delete duplicate decl and impl defines. (#118843)Pravin Jagtap1-2/+0
2024-12-03Revert "[AMDGPU] Use COV6 by default (#118515)"Shilei Tian1-1/+1
2024-12-03[AMDGPU] Use COV6 by default (#118515)Shilei Tian1-1/+1
2024-12-02AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard (#117844)Matt Arsenault1-0/+10
2024-11-26AMDGPU: Verify f8f6f4 formats in assembler (#117826)Matt Arsenault1-1/+2
2024-11-25AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)Matt Arsenault1-0/+1
2024-11-21AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)Matt Arsenault1-0/+27
2024-11-18AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)Matt Arsenault1-0/+2
2024-11-14[AMDGPU][True16][MC] Implement V_CVT_PK_F32_FP8/BF8 (#116106)Joe Nash1-2/+4
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata1-1/+0
2024-11-05[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)Brox Chen1-2/+2
2024-11-05AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (...Matt Arsenault1-3/+4
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-4/+4
2024-09-30[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)Jay Foad1-2/+2
2024-09-28[AMDGPU] Use MCRegister. NFCCraig Topper1-7/+5
2024-09-24[AMDGPU] Remove unused VGPRSingleUseHintInsts feature (#109769)Scott Egerton1-18/+0
2024-09-20[llvm] Don't call raw_string_ostream::flush() (NFC)Youngsuk Kim1-1/+0
2024-08-22[AMDGPU] Correctly insert s_nops for dst forwarding hazard (#100276)Jeffrey Byrnes1-0/+12
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