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path: root/llvm/lib/Target/AMDGPU/SOPInstructions.td
AgeCommit message (Expand)AuthorFilesLines
5 days[AMDGPU] introduce S_WAITCNT_LDS_DIRECT in the memory legalizer (#150887)Sameer Sahasrabuddhe1-0/+7
2025-07-15[AMDGPU] Use S_ADD_PC_I64 for long branches in gfx1250 (#148961)Stanislav Mekhanoshin1-0/+10
2025-07-11AMDGPU: Implement s_wait_asynccnt and s_wait_tensorcnt for gfx1250 (#148292)Changpeng Fang1-0/+23
2025-06-29AMDGPU: support s_monitor_sleep on gfx1250 (#146293)Changpeng Fang1-0/+12
2025-06-24AMDGPU: Remove s_waitcnt from gfx1250 support (#145620)Changpeng Fang1-0/+2
2025-06-22[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (#145152)Stanislav Mekhanoshin1-0/+6
2025-06-21[AMDGPU] Rename call instructions from b64 to i64 (#145103)Stanislav Mekhanoshin1-0/+26
2025-06-20[AMDGPU] Add s_wait_xcnt gfx1250 instruction (#145086)Stanislav Mekhanoshin1-0/+10
2025-06-19AMDGPU/GFX12: Fix s_barrier_signal_isfirst for single-wave workgroups (#143634)Nicolai Hähnle1-0/+3
2025-06-02[AMDGPU] Add UniformBinFrag to SALU fminimum/fmaximum patterns. NFCI. (#142169)Jay Foad1-5/+5
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-2/+2
2025-04-11[AMDGPU] Set hasSideEffects=0 for SALU psuedos (#134487)amansharma6121-7/+9
2025-03-28[AMDGPU] (x or y) xor -1 -> x nor y (#130264)Ana Mihajlovic1-0/+14
2025-03-10[AMDGPU] Add GFX12 S_ALLOC_VGPR instruction (#130018)Diana Picus1-0/+7
2025-03-04[AMDGPU] Remove unused s_barrier_{init,join,leave} instructions (#129548)Mariusz Sikora1-40/+0
2025-01-10[AMDGPU] Remove s_wakeup_barrier instruction (#122277)Mirko Brkušanin1-12/+0
2024-12-14AMDGPU: Remove large, negative AddedComplexity from minimum/maximum patterns ...Matt Arsenault1-1/+1
2024-12-11[AMDGPU] Support s_endpgm_ordered_ps_done on GFX11 (#119230)Jay Foad1-2/+3
2024-11-06[AMDGPU] modify named barrier builtins and intrinsics (#114550)Gang Chen1-4/+6
2024-09-24[AMDGPU] Remove unused VGPRSingleUseHintInsts feature (#109769)Scott Egerton1-11/+0
2024-08-08AMDGPU: Support VALU add instructions in localstackalloc (#101692)Matt Arsenault1-2/+2
2024-07-25[LLVM][AMDGPU] Copy isConvergent from Pseudo to Real instructions (#99658)Acim Maravic1-0/+5
2024-07-01[AMDGPU][NFC] Make GFX*Gen records globally available. (#97291)Ivan Kosarev1-38/+28
2024-06-27[AMDGPU] Fix unwanted LICM/CSE of llvm.amdgcn.pops.exiting.wave.id (#96190)Jay Foad1-0/+11
2024-06-18[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)Ivan Kosarev1-1/+5
2024-05-31[AMDGPU] Copy Defs and Uses from Pseudo to Real Instructions (#93004)Fabian Ritter1-0/+10
2024-05-09[AMDGPU] Create AMDGPUMnemonicAlias tablegen class (#89288)Joe Nash1-7/+21
2024-05-07AMDGPU: Add mode register use to s_getreg_b32Matt Arsenault1-2/+3
2024-04-23[AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622)Jay Foad1-1/+1
2024-04-03AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC (#87537)Changpeng Fang1-39/+39
2024-03-20[AMDGPU] Copy SOP properties from pseudo to real. NFCI. (#85997)Stanislav Mekhanoshin1-0/+13
2024-03-15[AMDGPU] Simplify some uniform patterns. NFC. (#85407)Jay Foad1-9/+8
2024-03-06AMDGPI: Rename HasExpOrExportInsts to HasExportInsts. NFC (#84252)Changpeng Fang1-2/+2
2024-03-05AMDGPU: Define HasExpOrExportInsts for export instruction definitions. (#84083)Changpeng Fang1-0/+2
2024-03-05AMDGPU: Make s_wait_samplecnt(_bvhcnt) dependent on hasImageInsts, NFC (#83932)Changpeng Fang1-0/+4
2024-02-28AMDGPU/GFX12: Insert waitcnts before stores with scope_sys (#82996)Petar Avramovic1-0/+1
2024-02-20[AMDGPU] Try decoding instructions longest first. NFCI. (#82014)Jay Foad1-0/+3
2024-02-12AMDGPU/NFC: Remove some bits from TSFlags (#81525)Konstantin Zhuravlyov1-3/+0
2024-02-12AMDGPU: Don't allow s_barrier on gfx12 (#81317)Konstantin Zhuravlyov1-1/+2
2024-02-07[AMDGPU] Clean up and share SOP Real instruction definitions (#80990)Jay Foad1-207/+146
2024-02-07[AMDGPU] Remove unused multiclassJay Foad1-4/+0
2024-02-02[AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)Jay Foad1-53/+60
2024-01-22[AMDGPU] Remove s_set_inst_prefetch_distance support from GFX12 (#78786)Stanislav Mekhanoshin1-1/+1
2024-01-20[AMDGPU] Add GFX12 llvm.amdgcn.s.wait.*cnt intrinsics (#78723)Jay Foad1-7/+14
2024-01-19[AMDGPU] Misc formatting fixes. NFC.Jay Foad1-2/+0
2024-01-18[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)Jay Foad1-0/+7
2024-01-18[AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186)Jay Foad1-1/+4
2024-01-17[AMDGPU] Reapply 'Sign extend simm16 in setreg intrinsic' (#78492)Stanislav Mekhanoshin1-1/+1
2024-01-17[AMDGPU] Fix llvm.amdgcn.s.wait.event.export.ready for GFX12 (#78191)Jay Foad1-4/+4
2024-01-16Revert "[AMDGPU] Sign extend simm16 in setreg intrinsic" (#78372)Florian Mayer1-1/+1
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