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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
AgeCommit message (Expand)AuthorFilesLines
8 daysAMDGPU: Move getMaxNumVectorRegs into GCNSubtarget (NFC) (#150889)Matt Arsenault1-5/+0
2025-07-18[AMDGPU] Use SIRegisterInfo to compute used registers. NFCI (#149051)Diana Picus1-2/+4
2025-06-27AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)Matt Arsenault1-0/+4
2025-06-13Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#14...Diana Picus1-5/+0
2025-06-03[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#133242)Diana Picus1-0/+5
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus1-0/+16
2025-04-23Revert "[AMDGPU] Support block load/store for CSR" (#136846)Diana Picus1-16/+0
2025-04-23[AMDGPU] Support block load/store for CSR (#130013)Diana Picus1-0/+16
2025-03-12[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)Brox Chen1-0/+12
2025-02-25[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)Brox Chen1-2/+2
2025-02-07AMDGPU: Use default shouldRewriteCopySrc (#125535)Matt Arsenault1-5/+0
2024-10-21Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)Akshat Oke1-0/+8
2024-10-17[AMDGPU] Factor out getNumUsedPhysRegs(). NFC. (#112624)Stanislav Mekhanoshin1-0/+5
2024-10-15Revert "[AMDGPU] Serialize WWM_REG vreg flag (#110229)"Peter Collingbourne1-8/+0
2024-10-14[AMDGPU] Serialize WWM_REG vreg flag (#110229)Akshat Oke1-0/+8
2024-10-04AMDGPU: Do not tail call if an inreg argument requires waterfalling (#111002)Matt Arsenault1-0/+3
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan1-0/+5
2023-11-24[CodeGen] Make some includes explicit (NFC)Nikita Popov1-0/+2
2023-11-08[AMDGPU] Callee saves for amdgpu_cs_chain[_preserve] (#71526)Diana1-0/+5
2023-09-21[AMDGPU] [SIFrameLowering] Use LiveRegUnits instead of LivePhysRegs.Pranav Taneja1-3/+3
2023-08-03[PEI] Switch to backwards frame index elimination by defaultJay Foad1-4/+0
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault1-7/+10
2023-07-27[AMDGPU] Avoid CodeGen dependencies from AMDGPU/Utils and MCTargetDescReid Kleckner1-0/+5
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka1-10/+7
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-7/+10
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan1-0/+6
2023-05-26[AMDGPU] Add pass to rewrite partially used virtual superregisters after Rena...Valery Pykhtin1-0/+19
2023-05-16[LLVM][Uniformity] Improve detection of uniform registersSameer Sahasrabuddhe1-0/+7
2023-01-22Use llvm::popcount instead of llvm::countPopulation(NFC)Kazu Hirata1-1/+1
2022-12-20[AMDGPU] Replace getPhysRegClass with getPhysRegBaseClassCarl Ritson1-4/+0
2022-11-18PEI should be able to use backward walk in replaceFrameIndicesBackward.Alexander Timofeev1-1/+5
2022-11-15Revert D137574 "PEI should be able to use backward walk in replaceFrameIndice...Fangrui Song1-4/+0
2022-11-15PEI should be able to use backward walk in replaceFrameIndicesBackward.Alexander Timofeev1-0/+4
2022-10-07AMDGPU: Update SlotIndexes independently of LiveIntervalsMatt Arsenault1-6/+5
2022-09-12TableGen: Introduce generated getSubRegisterClass functionMatt Arsenault1-6/+4
2022-08-24[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCIAlex Richardson1-2/+0
2022-07-06[NFC][AMDGPU] Cleanup the SIOptimizeExecMasking pass.Thomas Symalla1-0/+2
2022-06-02AMDGPU: Move SpilledReg from MFI to SIRegisterInfoMatt Arsenault1-0/+11
2022-04-11AMDGPU/GlobalISel: Remove unused parameterMatt Arsenault1-7/+3
2022-03-14[AMDGPU] Restrict machine copy propagation from creating unaligned classesStanislav Mekhanoshin1-0/+5
2022-02-02AMDGPU: Implement isAsmClobberableMatt Arsenault1-0/+2
2021-12-01[AMDGPU] Add a regclass flag for scalar registersChristudasan Devadasan1-4/+14
2021-11-29[AMDGPU] Enable copy between VGPR and AGPR classes during regallocChristudasan Devadasan1-0/+4
2021-11-26[AMDGPU] Make vector superclasses allocatableChristudasan Devadasan1-0/+9
2021-11-04[AMDGPU] Do not add debug locations to the code inside prologueRamNalamothu1-4/+5
2021-10-27[amdgpu] Handle the case where there is no scavenged register.Michael Liao1-0/+4
2021-09-30[AMDGPU] move hasAGPRs/hasVGPRs into headerStanislav Mekhanoshin1-6/+12
2021-09-01[AMDGPU] Introduce RC flags for vector register classesChristudasan Devadasan1-0/+5
2021-08-25[NFC][AMDGPU] Reduce includes dependencies.Daniil Fukalov1-1/+0
2021-08-24[MachineCopyPropagation] Check CrossCopyRegClass for cross-class copysVang Thao1-0/+7
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