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path: root/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
AgeCommit message (Expand)AuthorFilesLines
7 days[AMDGPU] MC support for v_fmaak_f64/v_fmamk_f64 gfx1250 intructions (#148282)Stanislav Mekhanoshin1-0/+1
9 days[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin1-0/+1
10 days[NFC][TableGen] Change DecoderEmitter `insertBits` to use integer types only ...Rahul Joshi1-17/+1
2025-06-21[AMDGPU] Rename call instructions from b64 to i64 (#145103)Stanislav Mekhanoshin1-0/+1
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-1/+1
2025-05-08[AMDGPU][NFC] Get rid of OPW constants. (#139074)Ivan Kosarev1-28/+7
2025-05-08[AMDGPU][Disassembler][NFCI] Always defer immediate operands. (#138885)Ivan Kosarev1-13/+5
2025-04-18[LLVM][TableGen] Move DecoderEmitter output to anonymous namespace (#136214)Rahul Joshi1-32/+2
2025-01-14[AMDGPU][True16][MC] true16 for v_cmp_lt_f16 (#122499)Brox Chen1-0/+1
2025-01-03[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)Jun Wang1-0/+1
2024-11-25AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)Matt Arsenault1-0/+1
2024-11-21AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)Matt Arsenault1-0/+1
2024-06-18[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)Ivan Kosarev1-0/+7
2024-04-18 [AMDGPU] Add disassembler diagnostics for invalid kernel descriptors (#87400)Emma Pilkington1-12/+13
2024-02-26[AMDGPU] Only try DecoderTables for the current subtarget. NFCI. (#82992)Jay Foad1-0/+1
2024-02-23[AMDGPU] Simplify AMDGPUDisassembler::getInstruction by removing Res. (#82775)Jay Foad1-9/+9
2024-02-22[AMDGPU] Split Dpp8FI and Dpp16FI operands (#82379)Jay Foad1-0/+1
2024-02-19[AMDGPU] Fix decoder for BF16 inline constants (#82276)Stanislav Mekhanoshin1-8/+13
2024-02-08[AMDGPU][True16] Support VOP3 source DPP operands. (#80892)Ivan Kosarev1-0/+1
2024-02-01[llvm-objdump][AMDGPU] Pass ELF ABIVersion through disassembler (#78907)Emma Pilkington1-0/+3
2023-12-13[AMDGPU] GFX12: Add Split Workgroup Barrier (#74836)Mariusz Sikora1-0/+1
2023-12-04[AMDGPU][MC] Add GFX12 VIMAGE and VSAMPLE encodings (#74062)Mirko BrkuĊĦanin1-0/+1
2023-10-12[AMDGPU] Change the representation of double literals in operands (#68740)Stanislav Mekhanoshin1-4/+5
2023-09-25[AMDGPU][NFC] Add True16 operand definitions.Ivan Kosarev1-0/+5
2023-09-23Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."Ivan Kosarev1-0/+11
2023-09-22Revert "[AMDGPU] Introduce real and keep fake True16 instructions."Ivan Kosarev1-11/+0
2023-09-22[AMDGPU] Introduce real and keep fake True16 instructions.Ivan Kosarev1-0/+11
2023-09-19[AMDGPU] Add ASM and MC updates for preloading kernargsAustin Kerbow1-0/+1
2023-07-06[AMDGPU] Improve assembler + disassembler handling of kernel descriptorsScott Linder1-0/+3
2023-06-29[NFC][AMDGPU] Refactor AMDGPUDisassemblerScott Linder1-0/+7
2023-06-25[llvm] Add missing StringExtras.h includesElliot Goodrich1-1/+2
2023-04-26[AMDGPU][Disassembler] Fix a spurious error message in an instruction comment.Ivan Kosarev1-2/+13
2023-02-01AMDGPU/MC: Refactor decoders. Rework decoders for float immediatesPetar Avramovic1-56/+7
2022-12-04[MC] llvm::Optional => std::optionalFangrui Song1-4/+3
2022-11-29[AMDGPU] Add support for new LLVM vector typesMateja Marjanovic1-0/+16
2022-10-07[AMDGPU][MC][GFX11] Correct v_fmac_.*_e64_dppDmitry Preobrazhensky1-0/+3
2022-09-21Revert "[NFC][AMDGPU] Refactor AMDGPUDisassembler"Scott Linder1-7/+0
2022-09-20[NFC][AMDGPU] Refactor AMDGPUDisassemblerScott Linder1-0/+7
2022-09-20[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,CJoe Nash1-0/+1
2022-07-15[AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op...Dmitry Preobrazhensky1-0/+1
2022-06-24[AMDGPU] gfx11 VOPD instructions MC supportJoe Nash1-0/+1
2022-06-09[AMDGPU] gfx11 VOPC instructionsJoe Nash1-0/+1
2022-06-08[AMDGPU] gfx11 VOP3P instruction MC supportJoe Nash1-0/+1
2022-06-07Reland [AMDGPU] gfx11 vop3dpp instructionsJoe Nash1-0/+55
2022-06-06Revert "[AMDGPU] gfx11 vop3dpp instructions"Joe Nash1-55/+0
2022-06-06[AMDGPU] gfx11 vop3dpp instructionsJoe Nash1-0/+55
2022-05-25[MCDisassembler] Disambiguate Size parameter in tryAddingSymbolicOperand()Maksim Panchenko1-2/+2
2022-05-25[AMDGPU] gfx11 vinterp instructions MC supportJoe Nash1-0/+1
2022-05-25[AMDGPU] gfx11 export instructionsJoe Nash1-0/+1
2022-05-18[AMDGPU][MC][GFX940] Correct tied operand decoding for smfmac opcodesDmitry Preobrazhensky1-1/+2
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